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Diode Reference Complementary Inverter Logic

IP.com Disclosure Number: IPCOM000100184D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+4]

Abstract

This circuit relates in general to fast BICMOS logic circuits. Based on the use of complementary bipolar and complementary FET transistors, it provides high circuit density and low power consumption at fast switching speed.

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Diode Reference Complementary Inverter Logic

       This circuit relates in general to fast BICMOS logic
circuits. Based on the use of complementary bipolar and complementary
FET transistors, it provides high circuit density and low power
consumption at fast switching speed.

      The figure shows, for instance, the circuit schematic of a
two-way NAND. It can be subdivided into three main parts:
1) The input stage (T3 to T6) that performs the logic function.
2) The ouput buffer (T1, T2) that provides the driving capability and
an invert function.
3) The DC bias voltage generator (T7 to T10 and D1, D2) that sets the
bases of T1 and T2 to a DC bias voltage that places T1 and T2
just at the limit of conduction (microamperes).

      The circuit shown in the figure is a two-way NAND:
-    when input A and/or B is down, the collector of T2 is tied to
the base through T5 or T6 and the output is maintained at the Ref. 2
voltage (2.8 V) through T8.
-    when both inputs A and B are up, the collector of T1 is tied
to the base through T3 and T4 and the output is maintained at the
Ref. 1 voltage (0.8 V) through T7. In both states T1 and T2 are
maintained at the limit conduction by the Ref. 1 and Ref. 2 bias
voltages by T7 and T8 which are in the On state.

      The D2/T10/T9/D1 chain is a simple voltage generator that
provides Ref. 1 and Ref. 2 voltages which track with the Vbe's of T1
and T2 to place them at the limit of conduction in standby. A
sufficiently low impedance is provided by the diodes even though the
consumed current can be kept very low using small width-to-length
ratios on T9 and T10.  T9 and T10 is an example of a device
combination that gives low current in a small silicon area. Other
combinations of PFETs and/or NFETs or a resistor can be used to
define this current. This bias generator can be shared by several
gates provided that they are located...