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Array Organization With Resistor Load MTL Cells

IP.com Disclosure Number: IPCOM000100186D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

Conventionally organized MTL (merged-transistor logic) array performance may be improved upon through the use of the new MTL array cell organization described in this article. Discharge loading is drastically reduced and discharge timing constraints relaxed, making possible fast arrays with superior cell density, soft error immunity and near zero power dissipation.

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Array Organization With Resistor Load MTL Cells

       Conventionally organized MTL (merged-transistor logic)
array performance may be improved upon through the use of the new MTL
array cell organization described in this article. Discharge loading
is drastically reduced and discharge timing constraints relaxed,
making possible fast arrays with superior cell density, soft error
immunity and near zero power dissipation.

      MTL cells, despite their superior density, soft error immunity
and cell power advantages over CTS (complementary-transistor logic)
cells, in general array applications, pose considerable difficulty to
the designer of high end array access.  Typically, in such
applications, discharge must be done for almost the whole array,
precisely after bit decode and before word decode.  Array access is
thus delayed, because the whole array (involving thousands of
picofarads) must be discharged and then charged in every cycle.  A
new MTL array with a new MTL cell avoids this difficulty in the
following manner:

      Fig. 1 illustrates the disclosed fast MTL array organization.
The array is 256 words x 160 bits (M groups of N cells; M =
N = 16, and L = 160); 16 HWs to select 1/16 word groups and
4 MWs and 4 LWs to select 1/16 words in a group.  As shown, N
cells of the same column share a common pair of subdiffusion beds,
I/O SBDs (Schottky Barrier Diodes) and pull-down resistors.  M groups
of these N cells are then coupled to the metal bit lines, where
conventional bit column sense/write/select circuits are connected,
making the layout much smaller and the bit line loading much lighter
than prior practice.  This approach drastically cuts down the
discharge loading and relaxes the discharge timing constraints,
thereby allowing high end array application. The operation is as
follows:
      1) STANDBY:    Word lines (WLs) are at fixed voltage levels
while current drain from word group lines (WGLs) determines cell
currents.  All SBDs are biased OFF .
      2) ACCESS:     Selected WGL and unselected WLs of the selected
group are discharged.
           READ:     The selected cell keeps one bit segment higher
than the other while they are both pulled down.  The differential
voltage is then coupled to the bit lines through the I/O = SBDs.
           WRITE:    One bit line is raised to force on side of the
MTL cell to turn...