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Packet Switching Module

IP.com Disclosure Number: IPCOM000100192D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Denzel, W: AUTHOR [+2]

Abstract

This article describes a concept for a buffered Fast Packet Switching module. In order to resolve contention at the output ports optimally, the switch comprises logical output queues which are allocated from a dynamically shared buffer pool. The approach bases on the separation of data and control, and it allows for a modular expansion of the buffer size.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Packet Switching Module

       This article describes a concept for a buffered Fast
Packet Switching module.  In order to resolve contention at the
output ports optimally, the switch comprises logical output queues
which are allocated from a dynamically shared buffer pool.  The
approach bases on the separation of data and control, and it allows
for a modular expansion of the buffer size.

      The figure shows the general structure of a switch with n input
and n output ports.  There are M Data Sections controlled by a single
Control Section.

      Each Data Section contains a set of shift registers as packet
storage.  A shift-register is supposed to hold one fixed-size packet
(e.g., ATM cell). At the input side, up to n incoming packets can be
routed simultaneously into free shift registers via individual
routers at each input.  The routing information for each of these
routers, i.e., a pointer to a free shift-register, is provided in
advance by the Control Section.  At the output side, up to n outgoing
packets can be transmitted simultaneously from appropriate shift
registers via individual selectors at each output. The select
information for each of these selectors, i.e., a pointer to full
shift registers holding packets due for transmission, is provided by
the Control Section, also.

      Modular storage expansion can be achieved by stacking multiple
data sections and interconnecting their inputs and outputs in
parallel.  Then, some bits of the address pointe...