Browse Prior Art Database

High Density Tantalum Oxide Capacitor DRAM Cell Structure And Process Outline for 64 Mb DRAM Chips And Beyond

IP.com Disclosure Number: IPCOM000100194D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 121K

Publishing Venue

IBM

Related People

Rajeevakumar, TV: AUTHOR [+2]

Abstract

A new DRAM cell with a tantalum pentoxide (Ta2O5) capacitor, and a process outline to fabricate this cell are disclosed. The proposed novel plasma enhanced chemical vapor deposition (PECVD) of Ta2O5, and low temperature processing avoid the usual problems of Ta2O5 capacitors, such as leakage and lowering of dielectric constant.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Density Tantalum Oxide Capacitor DRAM Cell Structure And Process Outline for 64 Mb DRAM Chips And Beyond

       A new DRAM cell with a tantalum pentoxide (Ta2O5)
capacitor, and a process outline to fabricate this cell are
disclosed. The proposed novel plasma enhanced chemical vapor
deposition (PECVD) of Ta2O5, and low temperature processing avoid the
usual problems of Ta2O5 capacitors, such as leakage and lowering of
dielectric constant.

      A schematic vertical cross section and top view of the proposed
new cell are shown in the figure.  A double polysilicon layer process
is necessary to realize this structure.  The tantalum pentoxide
capacitor is placed in a shallow trench about 3 mm deep.  Poly I is
the gate of the transfer device.  The access device is 3 mm long and
about 1 mm wide.  Poly II and tungsten metal form the capacitor
electrodes.  Poly II makes contact with the source of the access
device, and the tungsten metal is the capacitor plate common to all
the cells in the array.  A layer of silicon nitride isolates the
access device from the tantalum pentoxide capacitor.  A self-aligned
contact process is used to make contact with the drain and the
bitline.  The bitlines are formed using metal (M2), after the storage
capacitor has been fabricated.

      Process Outline: The cell fabrication procedures are given
below.  In this process sequence, an N-array with CMOS peripherals is
assumed.  The process can easily be modified for a P-array.
(1) P-substrate with about 1 ohm-cm resistivity is to be used.
Isolation oxide for device isolation (ROX, or other forms of
isolation) is grown and patterned using the ROX mask, and the
source/drain I/I of the access device at the top of the trench is
completed. 25 nm of SiO2, 100 nm of silicon nitride, and 500 nm of
SiO2 is blanket deposited by LPCVD techniques.  Shallow trenches,
about 3 mm deep, are then etched on the substrate using RIE.
(2) After the shallow trenches are etched, 10 nm gate oxide is
formed, followed by 100 nm of gate poly (poly I) deposition.  The
poly gate is defined by RIE.  The excess poly on the sidewall of the
trench is removed by wet etching, after masking the gate poly.  About
50 nm of blanket silicon nitride is deposited either by a PECVD
technique or by LPCVD.  The Si3N4 over the bottom of the shallow
trench and over other junction area is removed by anisotropic RIE.
This is followed by the I/I of the access device source/drain at the
bottom of the shallow trench.
(3) 100 nm of n+ polysilicon (Poly II), 15 nm of Ta2O5, and 200 nm
of...