Browse Prior Art Database

Configurable Multi-Port Sram

IP.com Disclosure Number: IPCOM000100200D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Clemen, R: AUTHOR [+2]

Abstract

Very large-scale integration (VLSI) techniques allow implementing a microcomputer system on a few chips. This usually implies that logic and memory are integrated on a single chip. In order to develop such complex chips within a reasonable time, an automatic design system is desirable that includes a subsystem for generating memory array macros. High-speed processors in particular require a variety of embedded multi-port (n-port) registers. Such a register comprises n address and n I/O ports for performing n write and read operations in a single cycle.

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Configurable Multi-Port Sram

       Very large-scale integration (VLSI) techniques allow
implementing a microcomputer system on a few chips.  This usually
implies that logic and memory are integrated on a single chip.  In
order to develop such complex chips within a reasonable time, an
automatic design system is desirable that includes a subsystem for
generating memory array macros.  High-speed processors in particular
require a variety of embedded multi-port (n-port) registers.  Such a
register comprises n address and n I/O ports for performing n write
and read operations in a single cycle.

      To shorten the development time for a family of multi-port
SRAMs, a semicustom design method is proposed which uses standard
cells and building blocks to compile a particular n-port macro for
any user- specified width or depth.  Instead of doing a full custom
design for each of the required macros, only the largest n-port macro
is optimized for density and performance, whereas the other m-port
RAMs (m < n) are assembled from the same basic circuit blocks by
deactivating or dropping the unnecessary ports.  The individual
circuits, particularly the n-port memory cell and the decoder, are
designed such that they can be easily reconfigured to satisfy a wide
range of applications.

      A fully static multi-port RAM cell, for instance, can be
implemented by using a static latch as a storage element and
attaching n ports each connected to a bit line BL and a word line WL.
 The CMOS embodiment features a cross-coupled CMOS inverter pair used
as a latch and n transfer NFETs arranged in single-ended connection,
one write port NFET, for example, being attached to the left (true)
latch node and a buffer (inverter) with n-1 read port NFETs being
attached to the right (complementary) latch node.  For a dense and
structured layout, the word lines are realized by first metal lines
extending horizontally and the bit lines as well as the power buses
by first metal lines extending vertically.

      The figure shows the new standard cell design method for a
two-port SRAM cell (1 write port, 1 read...