Browse Prior Art Database

Silicon Carrier Mounting

IP.com Disclosure Number: IPCOM000100210D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Schettler, H: AUTHOR [+2]

Abstract

Two identically processed silicon layers are bonded back-to-back. One layer acts as a chip carrier and the other as an I/O interface to the next packaging level. Such a structure avoids warping and allows various packaging technologies.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Silicon Carrier Mounting

       Two identically processed silicon layers are bonded
back-to-back.  One layer acts as a chip carrier and the other as an
I/O interface to the next packaging level.  Such a structure avoids
warping and allows various packaging technologies.

      Metal and isolation layers on top of large silicon layers warp
the silicon layer owing to different coefficients of expansion.  As a
result, the size of the silicon layers is limited, the reliability is
impaired and the packaging interface to the outside is difficult to
realize.

      As shown in the figure, two silicon layers 1 and 2 are back-to-
back bonded by gluing or eutectic molding.  Top layer 1 has several
metal planes 3 serving as connectors for power and signal
distribution, which are interconnected by vias.  Several chips 4, 5,
6 are mounted on top of silicon layer 1.  Silicon layer 1 has I/O
pads 7 on its entire periphery, which are preferably symmetrically
and periodically placed.

      The bottom silicon layer 2 is designed as a connection layer.
It is processed similarly to top layer 1.  The bottom-most metal
plane 8 connects the peripheral pads 9 to I/O pads 10 located in the
center.

      Silicon layers 1 and 2 are electrically connected along the
periphery by tabs 11 connecting pads 7 and 9.  The tabs may be single
tabs, split tabs, connector clips, wires or vias extending through
the two layers 1 and 2.

      This new silicon layer mounting is hi...