Browse Prior Art Database

Cell Restore Concept For MTL Arrays

IP.com Disclosure Number: IPCOM000100213D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 157K

Publishing Venue

IBM

Related People

Wendel, DF: AUTHOR [+2]

Abstract

A significant simplification of the relatively complex restore circuit now in use with MTL (merged transistor logic) arrays is achieved through application of the new restore concept described in this article. Accurate restore levels are obtained without the use of additional reference cells presently required.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Cell Restore Concept For MTL Arrays

       A significant simplification of the relatively complex
restore circuit now in use with MTL (merged transistor logic) arrays
is achieved through application of the new restore concept described
in this article.  Accurate restore levels are obtained without the
use of additional reference cells presently required.

      The size of the cell current in MTL arrays (Fig. 1) is defined
by the voltage appearing across the base-emitter junction of the
injector-PNP transistor (emitter connected to bit line 4, base
connected to word line 3).  The PNP transistor of the MLT cell can
operate both in forward and in reverse direction.  If the bit line is
pulled down by the selected cell (read/write operation), the bit line
potential will be lower than the potential at one of the internal
cell nodes and a current will be injected from the unselected cells
to either the left or right bit line, depending on the state of the
cell flip-flop.  Assuming the same data to exist in all unselected
cells, all back injected currents will flow into one bit line.  This
action hampers the build-up of a difference signal at the bit line,
resulting in increased access time.  Cell stability is also decreased
because the balance existing between left and right bit lines is
disturbed.

      The present restore circuit 11 insures that the voltage 7
across the base-emitter junction of the PNP-injector does not
increase above its well-defined standby value, an operation detailed
in U.S. Patent 4,334,294.  The standby cell current is defined by the
fixed voltage 2 established between word reference line 3 and bit
reference line 4.  Since bit switch transistor 5 and word transistor
6 are operated in deep saturation during standby, the voltage of bit
and word lines equals the potential at word reference line 3 and bit
reference line 4, respectively.  The voltage 2 is derived from the
voltage 7 generated across reference cell(s) impedance 8 by the
constant cell current 9.  The value of 9 is chosen to equal the value
of the required standby cell current times the number of reference
cells connected in parallel.  Since the cell standby current is
extremely small (about 10 - 50 nA), a large number of reference cells
have to be connected in parallel to decrease the output impedance of
the reference voltage generator 9, 8.  The large number of reference
cells (1500 for a 20K-byte array) needed with this approach to define
a sufficiently accurate reference voltage can be avoided by the
scheme shown in Fig. 2, in which 2 out of 32 subarrays of an MTL-RAM
with SE-Cell are shown.

      Very dense arrays have been demonstrated to be capable of
faster operation times, smaller discharge/restore currents and
minimized power dissipation, through partitioning into smaller
subarrays.  For example, a 256K-byte SRAM with MTL-SE-Cell (merged
transistor logic - split emitter - cell) may be divided into 32
subarrays, each having...