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Two-Phase/Extendable Input Bi-CMOS Multiplexer With Pass Transistors

IP.com Disclosure Number: IPCOM000100214D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+2]

Abstract

In BI-CMOS technology, complex logic functions are built from basic traditional NAND and NOR BI-CMOS circuits. Multiplexers are widely used in logic parts of data-processing chips (ALU, CONTROL, etc.). For example, to build a two input/two phase multiplexer 4 NAND 2 ways are necessary. The proposed BI-CMOS Multiplexer, based on pass transistors, is built with a reduced number of transistors and consumes a reduced silicon area to perform the same logic function. The figure shows an improved multiplexer circuit implemented with pass transistors.

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Two-Phase/Extendable Input Bi-CMOS Multiplexer With Pass Transistors

       In BI-CMOS technology, complex logic functions are built
from basic traditional NAND and NOR BI-CMOS circuits. Multiplexers
are widely used in logic parts of data-processing chips (ALU,
CONTROL, etc.).  For example, to build a two input/two phase
multiplexer 4 NAND 2 ways are necessary.  The proposed BI-CMOS
Multiplexer, based on pass transistors, is built with a reduced
number of transistors and consumes a reduced silicon area to perform
the same logic function.  The figure shows an improved multiplexer
circuit implemented with pass transistors.

      As shown in the figure the circuit is based on the use of pass
transistors in conventional CMOS logic followed by a BI-CMOS inverter
using NPN transistors for the driving capability.

      Due to the use of pass transistors (transfer gates), the
BI-CMOS circuit operates with full power supply voltage swing.
Devices TG1,TG2, etc., provide the multiplex function between Data1
(D1), Data2 (D2), etc., and the Clocks (C1,C2, etc.).  A latch
circuit is built with the CMOS transistors P1,P2,N1,N2 to provide
full swing CMOS levels at the input of the two BI-CMOS inverters (not
to degrade the performance and the levels); otherwise, the level is
degraded by a Vt on node A.  In a regular mode, one of the data
is transmitted to the output when the corresponding clock input rises
to 1 (ON state).  When both clocks are at zero, the 2 ouput sign...