Browse Prior Art Database

Basic Internal Cell for a BI-CMOS Circuit Family

IP.com Disclosure Number: IPCOM000100215D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+4]

Abstract

There is disclosed a new cell arrangement which has been designed for BI-CMOS circuits. It has prediffused elements to give the best silicon integration for a complete logic family, coupled with a fast turn- around time.

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This is the abbreviated version, containing approximately 52% of the total text.

Basic Internal Cell for a BI-CMOS Circuit Family

       There is disclosed a new cell arrangement which has been
designed for BI-CMOS circuits.  It has prediffused elements to give
the best silicon integration for a complete logic family, coupled
with a fast turn- around time.

      The particular cell layout based on the use of CMOS transistors
mixed with NPN bipolar transistors is also described in this article.
 The master slice cell has been optimized for the silicon
implementation of a complete BI-CMOS circuit logic family.  The
BI-CMOS logic circuit family disclosed herein is based on the
Multi-Base BI-CMOS circuit, as described in published European Patent
Application No. 0318 624.  The proposed cell has prediffused devices
which permit a late metal personalization for Turn-Around Time (TAT)
saving and cost reduction.

      A complete logic family including NAND, NOR, AND, AOI, OAI,
XOR, latches, etc., can be implemented on the same device background.
 The basic circuit of the logic family is a Multi-Base NAND shown in
Fig. 1.  Based on the statistical use of each circuit in VLSI chips,
the number of element in the basic cell can be optimized.  The
resulting cell has the following elements:
      large PFET:  6
      small PFET:  4
      large NFET:  8
      small NFET:  2
      NPN:         4

      The cell built with the optimum choice of devices is shown in
Fig.  2 before personalization.  The wired cell giving a NAND with 2
inputs is shown in Fig....