Browse Prior Art Database

High-Speed Counter

IP.com Disclosure Number: IPCOM000100216D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 122K

Publishing Venue

IBM

Related People

Buttimer, MD: AUTHOR [+3]

Abstract

Until recently, prescalers and high-speed phase-locked loop counters, operating in the hundreds of megahertz, were always designed in emitter-coupled logic. Such designs use vast amounts of power and often use unusual power supplies. This disclosed circuit design overcomes these problems by allowing the use of CMOS technology at very high frequencies. This is achieved by a novel technique of scrambling the value which was supposed to be loaded into the counter. A knowledge of counter design is assumed.

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High-Speed Counter

       Until recently, prescalers and high-speed phase-locked
loop counters, operating in the hundreds of megahertz, were always
designed in emitter-coupled logic.  Such designs use vast amounts of
power and often use unusual power supplies. This disclosed circuit
design overcomes these problems by allowing the use of CMOS
technology at very high frequencies.  This is achieved by a novel
technique of scrambling the value which was supposed to be loaded
into the counter.  A knowledge of counter design is assumed.

      In a conventional high-speed loadable counter, there are
several stages of gating between each stage of the counter.  In
commercially available counters, the design is usually identical.
The only difference is that the gates used are either NAND or NOR,
depending upon which is the faster in the technology.  In the circuit
described herein, the longest path, has a 2 input exclusive OR gate
and a 1 of 2 selector.  In the latest CMOS technologies, the
propagation delay of these two stages, would be in the order of 2
nanoseconds.  The propagation delay through a D-type bistable
multivibrator, would be in the order of 2 nanoseconds with a set up
time of 1 nanosecond.  Adding these together, 2 + 2 + 1 = 5
nanoseconds, suggests that the counter could be run at up to 200
megahertz.  To reduce the number of gate stages down to two by
conventional methods appears to be impossible.  To speed up
synchronous designs, pipelining the design (putting in more
synchronization stages) is the usual technique.  With a counter,
since the pipelining stages have to be reset when the counter reaches
terminal count, no gate stages can be removed.  The novel feature of
this counter is that the value loaded into the counter is a scrambled
version of the programmed value.  By using this technique, the upper
stages of the counter can be pipelined, without the need to be reset.

      Circuit Description: The counter shown in Fig. 1 is a seven-bit
down counter, though any number greater than two bits could be used.
It counts down from a predetermined value held in a register.  Once
the counter...