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Depleted Implant MOSFET

IP.com Disclosure Number: IPCOM000100218D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15

Publishing Venue

IBM

Related People

Vinal, AW: AUTHOR

Abstract

An enhancement MOSFET design and self-aligned method of fabrication are described, in which the design has low and controlled threshold voltage properties. This new design, called the Depleted Implant MOSFET, or simply "DI-MOSFET", eliminates a complex threshold voltage term characteristic to the operation of conventional enhancement MOSFET designs. The origin of the unwanted threshold voltage term is the voltage developed across the gate oxide layer necessary to establish inversion in conventional MOSFETs.

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Depleted Implant MOSFET

       An enhancement MOSFET design and self-aligned method of
fabrication are described, in which the design has low and controlled
threshold voltage properties.  This new design, called the Depleted
Implant MOSFET, or simply "DI-MOSFET", eliminates a complex threshold
voltage term characteristic to the operation of conventional
enhancement MOSFET designs. The origin of the unwanted threshold
voltage term is the voltage developed across the gate oxide layer
necessary to establish inversion in conventional MOSFETs.

      The DI-MOSFET allows punch-through prevention by raising
substrate doping in short channel devices without affecting threshold
voltage.  The DI-MOSFET is relatively simple to construct, promises
high wafer yields, and offers much simpler design ground-rules for
conventional and high-speed CMOS logic and analog circuits. The
"Depleted Implant" concept is applicable to both P and N-channel
MOSFET devices.

      A conventional enhancement MOSFET requires gate voltage to
induce an inversion layer of minority carriers that conduct current
between the source and drain.  A gate threshold voltage condition is
achieved when the surface potential ds of the substrate below the
gate is elevated sufficiently to bend the intrinsic energy band of
the semiconductor material down below the Fermi level.  This rise in
substrate surface potential is the result of increasing gate voltage
Vg which induces a depletion layer with depth Wdo in the substrate
below the gate.  From Poisson's equation the potential rise across
the depletion layer is
ds = (q/2es)(NaWdo2).
Depletion depth Wdo is defined as
Wdo =  (2esds/(qNa)).
The electric field at the substrate surface is Es =  (2ds qNa/es).
When the surface potential ds reaches twice the Fermi potential 2df,
minority carrier concentration Np within a P-substrate becomes equal
to the substrate acceptor concentration Na.  Surface potential ds
need only be increased slightly above threshold voltage 2df in order
to achieve inversion.  Unfortunately, charge is accumulated on the
gate as a result of creating the depletion layer.  The density of
this gate charge is qNaWdo coulombs per cm2 . Gate threshold voltage
Vt is the sum of the voltage developed across the gate oxide layer
and the rise in substrate potential 2df .  The gate oxide field is
qNaWdo/ei and the voltage Vox is qNaWdo/ci where Ci = ei/Tox .
Therefore: (1)

                            (Image Omitted)

where ds = 2df .
L* =  Effective channel length.

      When voltage is applied to the drain and source diffusions, a
potential V(X) is introduced at position X along the channel between
the drain and source.  The oxide threshold voltage term in (1)
increases with voltage V(X) in accordance with (2). (2)

      The threshold voltage contribution due to gate charge (2) is
complex and causes difficulties in both digital and analog circuit
design and device fabricati...