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Browse Prior Art Database

Low-Inductance Multilayer Ceramic Module

IP.com Disclosure Number: IPCOM000100222D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Frech, R: AUTHOR [+4]

Abstract

The article describes a method of reducing the effective inductance of MLC (multilayer ceramic) off- or on-module nets by means of specific viahole patterns. This allows faster simultaneous switching at higher dI/dt values. The low-inductance module thus obtained is comparable to future thin-film chip carriers.

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Low-Inductance Multilayer Ceramic Module

       The article describes a method of reducing the effective
inductance of MLC (multilayer ceramic) off- or on-module nets by
means of specific viahole patterns.  This allows faster simultaneous
switching at higher dI/dt values.  The low-inductance module thus
obtained is comparable to future thin-film chip carriers.

      As shown in Fig. 1, the power and ground vias are vertically
arranged below the chip site, extending the chip footprint C4's to
the MLC power and ground mesh planes.  The signal AC current Is1 has
two AC return current paths, one through power Ip1 and one through
ground Ig1.  They carry the AC current in almost identical magnitude,
as power and ground are tightly coupled by on-module and on-card
capacitors.  The AC currents have relatively large loops. Because of
the size of these loops, the effective inductance is not at its
minimum value and should be reduced further to permit fast
simultaneous switching at higher dI/dt values.

      As shown in Fig. 2, the signal path carrying the AC current Is1
has two AC return current paths Ig1 and Ip1 which are much closer
than in the arrangement of Fig. 1. Such close paths are obtained by
introducing additional viaholes which connect the power mesh planes
and the ground mesh planes, respectively.  As shown in Figs. 3 and 4,
the paths are arranged closely adjacent to the wiring of the signal
line fan-out from the chip C4 pads.  Fig. 4 shows eight AC retur...