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Wiring Redundancy On Silicon Chips And Chip Carriers

IP.com Disclosure Number: IPCOM000100232D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Beck, S: AUTHOR [+4]

Abstract

The wires of the main level of a multilayer wiring struc- ture on chips or chip carriers may be made largely redundant by providing identical copies on another level. Lateral shorts are reduced by optimizing lateral wire spacings at the expense of wire widths.

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Wiring Redundancy On Silicon Chips And Chip Carriers

       The wires of the main level of a multilayer wiring struc-
ture on chips or chip carriers may be made largely redundant by
providing identical copies on another level.  Lateral shorts are
reduced by optimizing lateral wire spacings at the expense of wire
widths.

      Normally, chip wires are designed such that defects (large
width) and lateral shorts (large lateral spacing) are minimized.

      For products having a size approximately or equalling that of a
full silicon wafer, the wiring according to the invention may be
optimized by having maximum lateral wire spacings but smaller wire
widths.

      For reducing the number of wire defects resulting from
micrometer defects and in particular large-area defects, all wires
are superimposed on or covered by identical wires on the respective
other level, space permitting.  Wires and their redundant copies are
frequently connected by vias.

      As in low-density structures most of the wires are arranged on
the same level, with the respective other level being used for
underpasses, redundant copies of the largest part of the wire length
may be provided on the respective other level.

      Large-area defects, leading to defects when a wiring level is
prepared, may thus be remedied by providing redundant wire lengths on
another level.
      Two variants are illustrated in the figure.
      1.   Normal layout of wiring with a part...