Browse Prior Art Database

Image Processor for a Professional Workstation

IP.com Disclosure Number: IPCOM000100237D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 6 page(s) / 187K

Publishing Venue

IBM

Related People

Gonzalez, MJ: AUTHOR [+2]

Abstract

This invention presents the most important design aspects of a serial processor which has been designed and built for the purpose of providing image processing functions to an existing professional workstation. The processor can handle binary, gray-level and color images. A prototype system consisting of this processor and a PC-AT as a host processor has shown better performance figures than the IBM 7350 image processor in most tested image processing algorithms. The architecture allows the implementation of algorithms like FFT, general geometric transformation, and algorithms that are serial in nature (like line followers). These algorithms are not suitable for the 7350 architecture.

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Image Processor for a Professional Workstation

       This invention presents the most important design aspects
of a serial processor which has been designed and built for the
purpose of providing image processing functions to an existing
professional workstation.  The processor can handle binary,
gray-level and color images.  A prototype system consisting of this
processor and a PC-AT as a host processor has shown better
performance figures than the IBM 7350 image processor in most tested
image processing algorithms.  The architecture allows the
implementation of algorithms like FFT, general geometric
transformation, and algorithms that are serial in nature (like line
followers).  These algorithms are not suitable for the 7350
architecture.

      A general block-diagram of the processor is given in Fig. 1.
The processor consists of a CPU with separated instruction and data
storages.  The connection to the workstation (host) is made through
the I/O Adapter.  The I/O Adapter contains the host interface (host
dependent), and a Control-Status Register (CSR) which is accessible
by the host CPU.

      Figs. 2 and 3 depict two different ways of connecting the
processor to the workstation.  The way shown in Fig. 2 assumes a host
bus with multi-master capability, i.e. the host CPU and the processor
CPU can access the bus under control of a bus arbiter.  Fig. 3
depicts how the processor is connected when the host bus does not
support multi- master operation.  A two-ported host memory is
required. One of the two memory ports is dedicated to the image
processor.

      The operation of the processor is as follows:  The processor is
a serial processor with separate instruction and data storages.  The
processor sees its local data storage and host memory as part of the
same address space. Image data is stored typically in host memory.

      When the processor is in the stop state, the host has access to
the CSR and to both the instruction storage and the local data
storage. Programs and parameters are transferred by the host CPU to
the processor when in this state.  When the processor is in the
running state, only the CSR is accessible to the host CPU.  The
processor informs the host CPU that the loaded program has been
executed by issuing an interrupt.

      Major design decisions and its implications are given below:
(1)  Serial Processor A serial processor architecture has been
selected to achieve maximum flexibility.  Algorithms requiring random
access to the image storage (like geometric transformations, median
filtering, line following, etc.) and those in which an output pixel
value is a function of previous results (as in recursive filtering)
are able to be implemented.
(2)  RISC Architecture The Reduced Instruction Set architecture
contains 16 general- purpose registers (R0 through R15).  All
operations are between registers.  Load and Store instructions
transfer data between Data Storage and general...