Browse Prior Art Database

Multimode Signalling Memory for High-Speed Time-Division Multiplexing

IP.com Disclosure Number: IPCOM000100240D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 7 page(s) / 334K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

A technique is described whereby transmit and receive random-access memory (RAM) is used for bit-oriented, or message-oriented, multimode signalling. The concept is particularly applicable in high-speed time- division multiplexing (TDM). Described is the use of RAM to solve both bit- and message-oriented signalling intricacies for North American (T1) and European modes (CEPT30), although the concept is not confined to these modes.

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Multimode Signalling Memory for High-Speed Time-Division Multiplexing

       A technique is described whereby transmit and receive
random-access memory (RAM) is used for bit-oriented, or
message-oriented, multimode signalling.  The concept is particularly
applicable in high-speed time- division multiplexing (TDM).
Described is the use of RAM to solve both bit- and message-oriented
signalling intricacies for North American (T1) and European modes
(CEPT30), although the concept is not confined to these modes.

      In digital TDM communications environments, data is sent from
point to point along with certain synchronization and alarm
indicators from transmitter to receiver.  The signalling bits must
have very specific decoding, as in on-hook/off-hook for telephone
applications.  In TDM applications, the signalling bit must be
synchronized with its time division; otherwise, an improper message
will be transmitted.  The concept described herein utilizes a
transmit RAM, a receive RAM, address generator and multiplexing
circuitry to control the signalling.

      Each signalling RAM is logically organized sixteen bits wide
and sixteen words deep.  For the North American (NAM) mode, the
contents of the RAMs, as shown in Fig. 1, utilize addresses '0010'
through '001F' for the circular buffer in a 4-KB/second data link.
In the receive circuitry, the appropriate bits within the T-1 frame
format are loaded into a shift register.  When eight bits have been
accumulated in the receiver, they are written to the receive RAM.
Data is taken from the transmit RAM eight bits at a time, and shifted
out as required by the Tx frame format.  An address counter is
incremented each time the RAM is accessed.  These addresses do not
correspond to the position of the data within the frame format, but
simply store the bits in the order in which they were received, or
retrieve bits from the transmit RAM in the order in which they must
be transmitted.

      Addresses 0000 through 000B are reserved for signalling (000C -
000F are not used).  The order in which the signals are transmitted,
or stored, are important.  'A' bits are accumulated from the sixth
frame, 'B' bits from the twelfth frame, 'C' from the eighteenth frame
and 'D' from the twenty-fourth frame.  A01 represents the 'A'
signalling bit for the first channel, A02 represents the 'A'
signalling bit for the second channel, and so on.  Therefore, the RAM
addresses identify the signalling bit for each channel.  In some
modes, only 'A' and 'B' signalling bits are required.

      In the European mode, there are two arrangements for the RAM,
as shown in Figs. 2 and 3.  In Fig. 2, the top half of the
RAM is reserved for a sixty-four KB/second data link similar to the
NAM mode. Typically, this arrangement would be applicable for the
Integrated Services Digital Network (ISDN).  The bottom half of Fig.
2 contains time slot zero (TS0) data which has synchronization and
alarm conditions...