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Browse Prior Art Database

Method of Simultaneously Defining Alignment Marks And Implantation Regions

IP.com Disclosure Number: IPCOM000100241D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Hagmann, D: AUTHOR [+2]

Abstract

When VLSI circuits are being produced, the wafer is normally structured with a basic alignment mark (zero level) to which successive layers are aligned. This requires a full photolithographic step and a subsequent RIE process.

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Method of Simultaneously Defining Alignment Marks And Implantation Regions

       When VLSI circuits are being produced, the wafer is
normally structured with a basic alignment mark (zero level) to which
successive layers are aligned.  This requires a full
photolithographic step and a subsequent RIE process.

      It is proposed that the basic alignment marks be defined
simultaneously by means of the mask used in the subsequent production
cycle, if the mask is an implantation mask.

      As shown in Fig. 1, both an adjustment mask 1 and an As+
implantation zone 2 to be produced in the first process step for the
actual semiconductor structure are defined and implanted in a resist
mask 3.  After a resist strip and drive-in process, a structure, as
shown in Fig. 2, is obtained, in which oxide I and oxide II are
formed simultaneously.  The oxide ratio (oxide I/oxide II) may be
arbitrarily changed by a suitable choice of implantation conditions
and oxidation temperature and time, so that the marking depth may
also be arbitrarily set.

      After the usual further process steps, a structure (Fig. 3)
with an alignment mark 1' and an implanted zone 2' is obtained.

      The advantage of this method is that a separate complete
masking step for producing the alignment marks is eliminated.