Browse Prior Art Database

Compression/Decompression for Memory Personalization

IP.com Disclosure Number: IPCOM000100263D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 169K

Publishing Venue

IBM

Related People

Kimmel, MJ: AUTHOR [+2]

Abstract

Disclosed is a method for rapid programming or personalization of writeable memories with logic table values. Electronically reconfigurable systems often use RAM chips for logic lookup. In such systems the addition of a hardware decompressor or personalization module, which itself can be personalized will facilitate transfer of logic table data from a host to the memories being personalized. The personalization module greatly reduces either table generation time or table storage size requirements in the host, since data can be stored and transmitted in compressed form. One compact form for logic tables is the data necessary to personalize the array of a writeable PLA.

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Compression/Decompression for Memory Personalization

       Disclosed is a method for rapid programming or
personalization of writeable memories with logic table values.
Electronically reconfigurable systems often use RAM chips for logic
lookup.  In such systems the addition of a hardware decompressor or
personalization module, which itself can be personalized will
facilitate transfer of logic table data from a host to the memories
being personalized. The personalization module greatly reduces either
table generation time or table storage size requirements in the host,
since data can be stored and transmitted in compressed form.  One
compact form for logic tables is the data necessary to personalize
the array of a writeable PLA.  The personalization module receives a
logic table from the host in PLA personality form from the host, and
uses the PLA to generate the full truth table for personalization of
a memory.

      The method applies directly to reconfigurable systems of which
the MITE is an example (1,2).  The method will also be applicable to
other bus-oriented systems which use memories to store and implement
logic switching functions.

      Figure 1 shows a typical system.  Without the personalization
module, personalization takes place thusly: A host system 1
communicates over a bus 0 to one or more memories of which the memory
3 is typical.  It does this by successively addressing each memory
address and supplying the data for that address.  There will also be
a multiplicity of bus interfaces containing line receivers 2 and
drivers 4, each serving either the host 1 or one or more programmable
memories 3.  Except for the addressing and the address decoding to
distinguish between groups of memories, and memories within groups,
the operations required to program each memory are identical.

      Adding the personalization module 5 and its own bus interface
6, the personalization is as follows:  The host system addresses the
personalization module input registers just as it would another
register or memory address in the system, and transmits to it the
compressed data which describes a logic table in PLA personality
form.  This PLA personalization is loaded into a writeable PLA in the
personalization module.  After this transfer is complete, the host
system is now free to continue processing.  The personalization
module takes over as a bus-master and sends the address data stream
to personalize the memory just as if such a stream were coming from
the host system.  The personalization module operates at hardware
speeds rather than at host processor speed, thus saving considerable
personalization time, even when the overhead of personalizing the
personalization module is taken into account.

      The details of the personalization module are shown in Fig. 2.
The host system first commands the control logic 5.5 to initialize
the personalization module PLA array 5.6. The control logic does this
by settin...