Browse Prior Art Database

Non-Contiguous Main Store Card Addressing Scheme

IP.com Disclosure Number: IPCOM000100275D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 100K

Publishing Venue

IBM

Related People

Eikill, RG: AUTHOR [+3]

Abstract

Described is a method which changes the way memory card addressing is performed. Memory cards are normally addressed in a contiguous fashion from the start address of any given card to the maximum address on that card. The main storage address region then moves to the next card and repeats this same pattern. This method describes a way of changing this addressing scheme so that as main storage addresses are incremented the actual card being accessed changes. The result is that now multiple memory cards are accessed in parallel rather than a single card performing multiple accesses. This method also allows for the address space of a single card or multiple cards, when interleaving, to be reconfigured by microcode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Non-Contiguous Main Store Card Addressing Scheme

       Described is a method which changes the way memory card
addressing is performed.  Memory cards are normally addressed in a
contiguous fashion from the start address of any given card to the
maximum address on that card.  The main storage address region then
moves to the next card and repeats this same pattern.  This method
describes a way of changing this addressing scheme so that as main
storage addresses are incremented the actual card being accessed
changes.  The result is that now multiple memory cards are accessed
in parallel rather than a single card performing multiple accesses.
This method also allows for the address space of a single card or
multiple cards, when interleaving, to be reconfigured by microcode.

      This method is intended to reduce contention for main storage
resource in a multi-processor system and add to the overall system
reliability by reconfiguring main store address region.  However, it
is not limited to this.

      A four-way interleave capability is provided for the first four
main store cards.  This interleave is intended for a multiprocessor
environment to reduce the amount contention that may arise when all
processors are requesting the same main store card which is done on a
512-byte basis. The interleave is enabled by properly programming a
configuration register.  MS cards 0-3 must all be the same size while
in interleave mode or must be configured as being the same size.  If
the cards are not the same size, the interleave may introduce holes
in main store.  These holes are page frames that can be deactivated
by software.

      Each main store card has its own set of configuration latches
implemented in a control chip.  The configuration latches contain two
fields.  The first defines the size of the main store card connected
to that physical slot, and the second defines the real address range
assigned to that slot. When interleaving is enabled, the card size
encode for main store cards 0-3 is set to four times the actual
physical card size of the cards in slots 0-3.

      When a main storage access is requested from the processor, the
control chip will reformat the real address sent from the processor
to a main storage address and a card select for a specific main store
card.  When interleaving is e...