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Method to Reduce Power in Partially Good Memory Chips

IP.com Disclosure Number: IPCOM000100283D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+4]

Abstract

By blowing a single fuse in a circuit following a word multiplexer, circuits related to operation of bad array elements are disabled very early in the data flow sequence. Thus, relatively simple programmed fuse blowing reduces power used in a partially good memory chip.

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Method to Reduce Power in Partially Good Memory Chips

       By blowing a single fuse in a circuit following a word
multiplexer, circuits related to operation of bad array elements are
disabled very early in the data flow sequence. Thus, relatively
simple programmed fuse blowing reduces power used in a partially good
memory chip.

      Referring to Fig. 1, true and complement (T/C) pulses from T/C
generator 10 come into word multiplexer (MUX) 14 and bit decode 12
via true and complement address lines 16. A fused circuit following
MUX 14 is detailed in Fig. 2 as an example of the method which may
also be employed in a circuit installed in bit decoder 12 or in a bit
multiplexer installed in series with bit address lines 18.  The fused
circuit provides means to disable circuits in sense amplifier timing
cir cuitry 20 as well as in input/output (I/O) circuits 22 following
word decoder 24.  Word decoder 24 output goes to timing circuit 20
via word line WL.

      Referring to Fig. 2, complement address line 16C comes into
word MUX 14 to transistor T8.  True address line 16T comes in to
transistor T9 and to transistors T1 and T2 of fused disable circuitry
26, then out to word decoder 24.  In normal operation, devices T8,
T1, T9, and T4 are on so as to receive address signals at word
address time and turned off at bit address time to trap word address
information in word decoder 24.  For a bad I/O array in a partially
good chip, transistors T1 and T4 are turned...