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Reduced Voltage Bit Line Restore Circuit

IP.com Disclosure Number: IPCOM000100285D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR

Abstract

By means of this voltage reducing circuit, support circuits may continue to be operated at a supply voltage of 5.0 volts while new complementary metal oxide silicon (CMOS) memory arrays may be operated at 3.3 to 3.4 volts for improved reliability.

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Reduced Voltage Bit Line Restore Circuit

       By means of this voltage reducing circuit, support
circuits may continue to be operated at a supply voltage of 5.0 volts
while new complementary metal oxide silicon (CMOS) memory arrays may
be operated at 3.3 to 3.4 volts for improved reliability.

      A typical CMOS dynamic random-access memory (DRAM) sense latch
is shown in Fig. 1.  Every bit line has an N-latch, transistors T4
and T5, and a P-latch, transistors T2 and T3. N-set device T6
discharges N-set bus 8 for a large number of sense latches and P-set
device T1 charges P-set bus 6 for a large number of sense latches.
Transistor T1 is a P channel device with a 0.0 volt level on its gate
during the time the P-set bus is charging.

      By means of the circuit shown in Fig. 2, the bit line pull-up
voltage level may be less than supply voltage VDD operating the
support circuitry.  The circuit of Fig. 2 may generate a voltage of
3.4 volts from VDD of 5.0 volts, for instance.  Reference voltage
generator 10 creates a DC potential V3 internally which is the level
to which bit lines BL and BLN (Fig. 1) charge. Generator 10 provides
DC potentials V3+Vt and V3-Vt to the circuit.  At the start of the
charge of P-set bus 6, node A falls to 0.0 volts since transistor T11
turns on and T12 is already on, as shown in the timing diagram of
Fig. 3, after delay by inverter I and  3-inverter chain 14.
Transistor T12 shuts off and shuts off the node A discharge path
thr...