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Bit Line Pull-Up Circuit for Static Ram 4-Device Cell

IP.com Disclosure Number: IPCOM000100299D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Coppens, P: AUTHOR [+4]

Abstract

This article describes a Bit Line Pull-up circuit designed for 4-device (4D)-cell RAM applications. It is useful in either CMOS or BI-CMOS technology. In 4D cell without poly-load resistor, the internal high node is floating and can be pulled down by different leakage currents, such as diffusion, sub-threshold current, etc. Thus, a refresh operation is recommended in order to prevent this problem and thus maintain the correct voltage in the cell. This internal voltage shift is critical and determines the sensitivity of the cell to alpha particles and leakage currents. Then, neither the Read nor the Write operation have to degrade this high level. To avoid a problem, a Bit Line Pull-up circuit is such a solution and is described hereafter.

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Bit Line Pull-Up Circuit for Static Ram 4-Device Cell

       This article describes a Bit Line Pull-up circuit
designed for 4-device (4D)-cell RAM applications. It is useful in
either CMOS or BI-CMOS technology. In 4D cell without poly-load
resistor, the internal high node is floating and can be pulled down
by different leakage currents, such as diffusion, sub-threshold
current, etc. Thus, a refresh operation is recommended in order to
prevent this problem and thus maintain the correct voltage in the
cell. This internal voltage shift is critical and determines the
sensitivity of the cell to alpha particles and leakage currents.
Then, neither the Read nor the Write operation have to degrade this
high level. To avoid a problem, a Bit Line Pull-up circuit is such a
solution and is described hereafter.

      Before describing the Bit Line Pull-up circuit, bearing
reference BLP, recall how a basic Write operation affects the
internal high level of a 4D cell, as referenced CELL in the data path
of Fig. 1. After the bit line restore circuit is turned off and the
correct data 'DT/DC' line is applied on the Write circuit - one bit
line being discharged (BLL) - the wordline 'WL' is selected. The
internal high node of the cell is then discharged through the
transfer gate "TXL' to the writing device, while the internal low
node begins to increase because of a current coming from 'BLR'. Next
'TCL' turns on, 'TCR' turns off and the two nodes A and B switch.

      Following the decrease of the potential on the high bit line,
the cell high node voltage decreases, as there is no pull-up device -
PFET or Resistor Load - on that 4D cell. Thus, the internal voltage
swing after writing (WVBA) is lower than the one before the write
operation (WVAB).

      Thus, at the beginning of a W...