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Improved 8-Bit Parallel CRC Generator-Checker Hardware Design

IP.com Disclosure Number: IPCOM000100300D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Dang, TH: AUTHOR [+2]

Abstract

Disclosed is an improved 8-Bit Parallel Cyclic-Redundancy-Check hardware design using the CRC-CCITT standard polynomial. The design is interfacing with a 16-Bit Bus. See the figure.

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Improved 8-Bit Parallel CRC Generator-Checker Hardware Design

       Disclosed is an improved 8-Bit Parallel
Cyclic-Redundancy-Check hardware design using the CRC-CCITT standard
polynomial.  The design is interfacing with a 16-Bit Bus.  See the
figure.

      The 8-bit parallel CRC equations can be obtained from (*).  The
clock for the feedback registers is the /WR signal, which is also
used to clock the data into the input register.  The INIT signal is
used to set the feedback registers to all HIGH.  The CRC output
register is actually a 16-bit tri-state data buffer with the /RD
signal being the control signal.  The invert-and-bit-reverse process
is done according to these equations:
Y0  = NOT  X7(n+1),   Y1  = NOT  X6(n+1),   Y2  = NOT X5(n+1),
Y3  = NOT  X4(n+1),   Y4  = NOT  X3(n+1),   Y5  = NOT X2(n+1),
Y6  = NOT  X1(n+1),   Y7  = NOT  X0(n+1),   Y8  = NOT X15(n+1),
Y9  = NOT X14(n+1),   Y10 = NOT X13(n+1),   Y11 = NOT X12(n+1),
Y12 = NOT X11(n+1),   Y13 = NOT X10(n+1),   Y14 = NOT X9(n+1),
Y15 = NOT  X8(n+1).

      To generate the CRC for transmission data, the feedback
registers are first initialized to all HIGH.  The 8-bit data bytes
are then written into the input register.  After the last byte has
been written, the 16 CRC bits of the transmission data are obtained
by reading the output register.  During the transmission, the data
are transmitted in their order, followed by the upper eight bits of
the CRC,...