Browse Prior Art Database

Processor Status Tool for Performance Analysis

IP.com Disclosure Number: IPCOM000100320D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 153K

Publishing Venue

IBM

Related People

Dietel, JD: AUTHOR [+6]

Abstract

A design of follow-on generations of central processors and the performance tuning of software applications and compilers requires information pertaining to the use of a central processor. As levels of integration increase, the likelihood increases that the information collected will be contained within a single chip and not be available externally to traditional hardware monitors. Collecting the data via software can be highly intrusive, affecting system performance and the data being collected. This information collection technique must minimize the perturbation in the computer system performance and the data being collected.

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This is the abbreviated version, containing approximately 38% of the total text.

Processor Status Tool for Performance Analysis

       A design of follow-on generations of central processors
and the performance tuning of software applications and compilers
requires information pertaining to the use of a central processor.
As levels of integration increase, the likelihood increases that the
information collected will be contained within a single chip and not
be available externally to traditional hardware monitors.  Collecting
the data via software can be highly intrusive, affecting system
performance and the data being collected.  This information
collection technique must minimize the perturbation in the computer
system performance and the data being collected.

      Periodic sampling triggered by a timer or counter supported by
the hardware can minimize the perturbation to system performance.
After such interrupts, an interrupt routine implemented in a
microcode layer executed by the hardware can glean the required
information.

      This method allows for the gleaning of any information
pertaining to the use of a processor which is available to a
Horizontal Microcode (HMC) layer executed directly by the hardware.
For many functions, the HMC can be thought of as the interpreter of
the instructions supported by the processor.  This process of
gleaning information is initiated with the expiration of a timer or
overflow of a counter.  At expiration or overflow, the first level
exception handler in HMC is entered, the requested information is
gathered and then saved in a buffer in main store.  If required, the
same type of information can be saved after each of up to "N"
contiguous instructions, after which point the processor returns to
normal instruction interpretation.

      The following discusses this process by looking at each portion
of this process which are:
      1.  Set-up and Invocation
      2.  Sampling Technique
      3.  Completion of Sampling

      The execution of a processor instruction initiates this
process.  The instruction passes to the processor the following:
      -  The type of information to be gleaned.
      -  The time interval or the number of instructions to
         execute between sample periods.
      -  The number of contiguous instructions during which
         information is to be gleaned.
      -  The address and size of the buffer in main store
         into which
         the gleaned data is to be saved.

      The process of gleaning information is ended when the buffer is
filled or when an instruction is executed which disables the process.

      The HMC microcode layer acts as an interpreter for the
instruction set supported by the processor and also supports a
first-level exception handler.  Among the responsibilities of this
exception handler are handling exceptions which are associated with
instruction interpretation and handling exceptions which are not
associate...