Browse Prior Art Database

Semiconductor Wafer Polishing

IP.com Disclosure Number: IPCOM000100335D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 1 page(s) / 26K

Publishing Venue

IBM

Related People

Esslinger, DC: AUTHOR [+2]

Abstract

Usable land areas on semiconductor wafers can be enlarged by using magnesium oxide as a protective layer during wafer processing.

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This is the abbreviated version, containing approximately 100% of the total text.

Semiconductor Wafer Polishing

       Usable land areas on semiconductor wafers can be enlarged
by using magnesium oxide as a protective layer during wafer
processing.

      In Fig. 1, wafer 1 with barrier layer 2 is coated with a 0.2
um thick layer 3 of magnesium oxide that is patterned as an etching
mask.  Wafer etching, ion implantation oxidation or other processes
are carried out.  The etched wafer surface is coated with spin-on or
chemical vapor deposited material 4 to fill the recessed areas.  This
process also covers the land areas.  Excess fill material is polished
off the small protruding lands and sufficiently removed by the
polishing operation to expose the edges 5 of the large land areas.
In Fig.  2, oxalic acid is used to remove the magnesium oxide.  This
leaves fill material 4 in the final structure while only lands are
cleared.