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Low Temperature Process for Making FET Devices Utilizing Copper Silicide (Cu3Si) As Contact And Interconnections Metallization

IP.com Disclosure Number: IPCOM000100336D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Aboelfotoh, MO: AUTHOR

Abstract

Disclosed is a low temperature process for making silicon FET devices which utilize copper silicide (Cu3Si) as contact and interconnections metallization.

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Low Temperature Process for Making FET Devices Utilizing Copper Silicide (Cu3Si) As Contact And Interconnections Metallization

       Disclosed is a low temperature process for making silicon
FET devices which utilize copper silicide (Cu3Si) as contact and
interconnections metallization.

      Referring to Figs. 1 through 4, a layer of copper having a
thickness of 2000 to 3000 angstroms is deposited over the entire
silicon substrate, as shown in Fig. 1, using a technique such as
electron-beam evaporation, magnetron sputtering, or chemical vapor
deposition.  The silicon substrate is then heated to temperatures in
the range from 175oC to 200oC for a time in the range from 20 minutes
to 30 minutes in an oxygen-free atmosphere to form copper silicide in
regions where copper is in contact with single crystal and
polycrystalline silicon, resulting in the structure shown in Fig. 2.
 This is followed by etching unreacted copper using excimer laser,
such as KrF at 248 nm or ArF at 193 nm, and selected Freon gases,
such as CF2Br2 .  In this process, etching occurs only in regions
where the laser light is striking the unreacted copper, as shown in
Fig. 3, allowing the use of a simple light-pattern-forming system.
The resulting structure after etching the unreacted copper is shown
in Fig. 4.

      The advantage of this process over prior art is that contacts
to source and drain regions and gate metallization are formed at low
temperatures.  Another advantage is that ...