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Extended Rotate And Merge Instructions With Built-In Masks

IP.com Disclosure Number: IPCOM000100367D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Flurry, GA: AUTHOR

Abstract

This technique provides for extended rotate and merge instructions with built-in masks. The need for such instructions arises in using a RISC CPU to emulate a CISC CPU. The RISC requires additional general- purpose registers (GPRs)and instructions beyond those available for Native operation to emulate the CISC with adequate performance. The RISC has a second "bank" of GPRs to provide additional fast storage used in emulation. The original register file of 32 GPRs is called bank 0 and the additional register file required for high-speed emulation is called bank 1. It is necessary to move information between the two banks. For additional speed, it is necessary to manipulate the data moving between banks via masks that allow placing specific parts of a GPR in specific parts of another GPR.

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Extended Rotate And Merge Instructions With Built-In Masks

       This technique provides for extended rotate and merge
instructions with built-in masks.  The need for such instructions
arises in using a RISC CPU to emulate a CISC CPU.  The RISC requires
additional general- purpose registers (GPRs)and instructions beyond
those available for Native operation to emulate the CISC with
adequate performance.  The RISC has a second "bank" of GPRs to
provide additional fast storage used in emulation.  The original
register file of 32 GPRs is called bank 0 and the additional register
file required for high-speed emulation is called bank 1.  It is
necessary to move information between the two banks. For additional
speed, it is necessary to manipulate the data moving between banks
via masks that allow placing specific parts of a GPR in specific
parts of another GPR.

      The Native RISC architecture executes rotate and merge
instructions that move data from one GPR in bank 0 to another GPR in
bank 0 with programmable rotation counts and programmable masks.
These instructions allow both an insert of the source into the target
and a simple movement of the masked source to the target.  The
instruction form for these Native rotate and merge instructions is
shown in Fig. 1. The rotation count is provided by a constant field
in the instruction (in bits 16-20, SH) or by a register identified in
the instruction (in bits 16-20, RB). The mask is defined by the two
fields in the instruction MB and ME (bits 21-25 and 26-30,
respectively).  Thus, the RISC contains the logic required to perform
the basic rotate and merge functions.  The Native forms require four
primary op codes (constant and register count forms for "insert under
mask" and "move with mask" forms).

      A conventional manner in which one could extend the Native
architecture to address the additional bank of GPRs is to use the
existi...