Browse Prior Art Database

True Complement Write Through Modes for Arrays

IP.com Disclosure Number: IPCOM000100377D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+2]

Abstract

Disclosed is a means to allow logic surrounding embedded arrays to be easily and completely tested. This method is useful in designs where there are multiple arrays receiving data from the same source and these arrays feed into a common logic.

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True Complement Write Through Modes for Arrays

       Disclosed is a means to allow logic surrounding embedded
arrays to be easily and completely tested.  This method is useful in
designs where there are multiple arrays receiving data from the same
source and these arrays feed into a common logic.

      Arrays in logic chips usually create testing problems. It is
typical to have a number of arrays which have a common source and
also have their outputs feed a common sink.  A problem is then posed
for testing the multiplexer (mux) or multi-port register which
receives its inputs from the different arrays.  Conventional array
write-through mode forces the array data output to be equal to the
array data input.  In this new method, an additional control input to
the arrays determines whether the write-through data output will be
inverted (the ones complement of the input data). The true/complement
write-through mode feature provides a means of testing the input
ports of the mux or the multi-port register fed from the array
outputs.  By leaving one array in true-write-through mode and putting
the other arrays in complement-write-through mode, the mux data
inputs can be set to any combination.

      The figure shows mux-1 sources the same bus to arrays 1, 2, 3
and 4.  Also, arrays 1, 2, 3 and 4 output buses feed the four input
ports of mux-2.

      It is not possible to test mux-2 using a simple array
write-through approach because all the arrays have one...