Browse Prior Art Database

Dynamic Storage Subsystem Path Switching

IP.com Disclosure Number: IPCOM000100390D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Bardsley, H, III: AUTHOR [+5]

Abstract

Advanced control unit architecture for direct access storage devices (DASDs) is based on parallel clusters of parallel storage path to provide better performance. Each cluster in the control unit connects to a set of channel attachment parts through a multiplexer that dynamically assigns access through an available storage path within the cluster to a DASD. Each storage path within the cluster connects to at least a subset of a set of DASDs serviced by the unit. A plurality of dynamic pathing memories, one located in each cluster, maintain a copy of the dynamic path control information for each storage path within all clusters. In the event one path fails, another path is able to recover access to the DASD based on its copy in the dynamic pathing memory.

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Dynamic Storage Subsystem Path Switching

       Advanced control unit architecture for direct access
storage devices (DASDs) is based on parallel clusters of parallel
storage path to provide better performance.  Each cluster in the
control unit connects to a set of channel attachment parts through a
multiplexer that dynamically assigns access through an available
storage path within the cluster to a DASD.  Each storage path within
the cluster connects to at least a subset of a set of DASDs serviced
by the unit.  A plurality of dynamic pathing memories, one located in
each cluster, maintain a copy of the dynamic path control information
for each storage path within all clusters.  In the event one path
fails, another path is able to recover access to the DASD based on
its copy in the dynamic pathing memory.

      The figure shows multiple control processing units (CPUs)
accessing a shared DASD with dynamic pathing as disclosed in U.S.
Patent 4,207,609.  The CPUs are connected to storage clusters 10 and
12 over channels.  The channels are connected to channel interfaces
14 located in each storage cluster.  Each storage cluster also
includes storage paths 16 and a dynamic pathing memory (DPM) 18.  The
outputs of the storage paths 16 are connected to the DASD controllers
20 which, in turn, are coupled to the storage devices 0-3 themselves
through sequence controllers (SCs) 22 and attachment logic blocks 24.

      The number of paths of connection between t...