Browse Prior Art Database

Snoop Mechanism to Monitor Computer Bus

IP.com Disclosure Number: IPCOM000100391D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Buttimer, MD: AUTHOR [+5]

Abstract

Normally, data traffic on a computer bus system is issued by a single source and is addressed to a single destination adapter for its exclusive use. The novel concept of a second adapter 'eavesdropping' on the bus for specific transmissions to carry out this function is the subject of this disclosure.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

Snoop Mechanism to Monitor Computer Bus

       Normally, data traffic on a computer bus system is issued
by a single source and is addressed to a single destination adapter
for its exclusive use.  The novel concept of a second adapter
'eavesdropping' on the bus for specific transmissions to carry out
this function is the subject of this disclosure.

      An example of such a situation is in the area of video displays
when a Personal Computer (PC) has a native display adapter already on
the base board.  The user may wish to add a high function display
adapter but is faced with task of emulating the native display.  The
particular problem of acquiring the palette contents passed by the
baseboard processor to the native display adapter can be solved using
the 'eavesdropping' principle, known as 'snooping the bus'. The use
of this mechanism will depend upon the applications involved as it is
generally applicable.  Generality is supported by the fact that it is
totally programmable and made faster by virtue of a small amount of
built-in control logic.

      The basic system diagram is shown in Fig. 1.  Two registers are
used to specify the range of the addresses to 'snoop':  The snoop
start address register defines the start address, and the snoop end
address register represents the end address of the range of addresses
to be monitored by this mechanism.  These addresses can be either I/O
or memory space addresses, and read and/or write accesses can be
'sno...