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Browse Prior Art Database

Interfacing Processor-based Devices to Personal Computing Systems

IP.com Disclosure Number: IPCOM000100403D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Baker, RG: AUTHOR [+7]

Abstract

A technique is described whereby processor-based devices are interfaced to the MICRO CHANNEL* of a personal computing system. The described architecture enables read and write operations to be performed to and from the data storage of a processor-based device. The following description centers on interfacing processor-based devices to the MICRO CHANNEL of a personal system; however, the same concept can apply to the bus of a personal computer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Interfacing Processor-based Devices to Personal Computing Systems

       A technique is described whereby processor-based devices
are interfaced to the MICRO CHANNEL* of a personal computing system.
The described architecture enables read and write operations to be
performed to and from the data storage of a processor-based device.
The following description centers on interfacing processor-based
devices to the MICRO CHANNEL of a personal system; however, the same
concept can apply to the bus of a personal computer.

      For the purposes of this concept, the term 'processor' refers
to microprocessor, digital signal processor and/or micro-controllers
which drive attachment devices accessing the MICRO CHANNEL or the PC
bus.  The processor device is assigned an address, or address range,
to which it can respond as an input/output (I/O) device.  When this
address, or range, is recognized along with the appropriate
combination of control signals, the following sequence is initiated:
   - Once an address is recognized, card (CD) channel ready (CHRDY)
signal is pulled inactive on the assumption that the transfer cannot
be completed during one standard MICRO CHANNEL cycle. This operation
is performed for variable length's of I/O commands.
     - For both read and write cycles, the information on the MICRO
CHANNEL address bus will be latched if the device responds to more
than one I/O address.  If only one address is ever recognized, it is
not necessary to latch the address.
     - A state machine is released from an initial idle state into
one which will detect the presence of an active direct memory access
channel (DMAC), which is a direct memory access (DMA) anticipate
signal from the processor.  This signal indicates that the cycle
following the current cycle is one in which the address and data
buses will not be used.  This allows the buses to be used for a DMA
transfer.
     - If the processor in question does not offer the DMAC feature,
the function may be created with added logic (not covered in this
write-up).  The additional logic would decode the opcodes as the
processor fetches them and determines if the upcoming instruction is
one which does not require the buses.
     - When the DMAC detect logic is enabled, a processor cycle
counter is also released from its idle state.  The final value of
this counter is a function of the application and the clock
frequencies being used.  If the counter reaches its final value
before a DMAC is detected, the DMA request (DMAR) line is pulled
active.  Activating DMAR forces the processor to free the address and
data buses to allow a transfer, thereby interrupting
       the execution flow of the processor.

      Several criteria must be considered in the determination of the
cycle counter duration.  For the maximum value determination, the sum
of the processor cycle times and the time for any overhead to be
performed before a CD CHRDY will be inactive mus...