Browse Prior Art Database

Double Emitter Logic in Bicmos Technology

IP.com Disclosure Number: IPCOM000100408D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+5]

Abstract

The present proposal, shown in the figure, is based on the use of complementary NPN and PNP emitter followers driven by CMOS logic. The high speed of the circuit is based on the fact that, in the CMOS part of the circuit, the pull-up devices are separated from the pull-down devices to perform the logic: node BN1 and BN2 drive node BP via small emitter followers that decouple their parasitic capacitances: - for the down-going transition, BP is not slowed down by crossover current and capacitance of devices P1 and P2 since nodes BN1 and BN2 are pulled down quickly by NU1 and NU2, at the speed of an inverter, which is faster than a NAND.

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Double Emitter Logic in Bicmos Technology

       The present proposal, shown in the figure, is based on
the use of complementary NPN and PNP emitter followers driven by CMOS
logic.  The high speed of the circuit is based on the fact that, in
the CMOS part of the circuit, the pull-up devices are separated from
the pull-down devices to perform the logic: node BN1 and BN2 drive
node BP via small emitter followers that decouple their parasitic
capacitances:
-    for the down-going transition, BP is not slowed down by
crossover current and capacitance of devices P1 and P2 since nodes
BN1 and BN2 are pulled down quickly by NU1 and NU2, at the speed of
an inverter, which is faster than a NAND.
-    for the up-going transition, output node OUT is not slowed down
by BP because BP is quickly pulled up by the emitter followers driven
from nodes BN1 and BN2 which, again, are switched up quickly by the
inverters.

      Basically, the disclosed circuit is based on the Multi-Emitter
BiCMOS concept as disclosed in published European Patent Application
No. 87480020.4.

      An OR pull-up logic is performed by emitter dotting of
transistors TN1 and TN2, while a NAND pull-down logic is performed by
connecting N FETs ND1 and ND2 in series.  It must be noted that the
bipolar OR pull-up logic is preceded by a CMOS inversion to perform
the equivalent NAND function.

      The output driving capability is provided by the bipolar
emitter followers TP, TN1 and TN2.

      Sources of FETs NU1 and NU2 are tied to a reference voltage
(Vref) instead of being connected to Ground in order to decrease the
voltage...