Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Measurement of Gate Level Line Foreshortening

IP.com Disclosure Number: IPCOM000100414D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Sheets, JE: AUTHOR

Abstract

A novel structure which allows accurate measurement of polysilicon (gate level) line shortening, often called foreshortening is described. Foreshortening is a situation where a physical line segment on a silicon chip is significantly shorter than the designer had intended. Polysilicon foreshortening has historically been a major source of functional AC and/or DC failures and a significant reliability inhibiter. This device demonstrates the feasibility of electrical measurement of gate level line foreshortening.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Measurement of Gate Level Line Foreshortening

       A novel structure which allows accurate measurement of
polysilicon (gate  level) line shortening, often called
foreshortening is described.  Foreshortening is a situation where a
physical line segment on a silicon chip is significantly shorter than
the designer had intended. Polysilicon foreshortening has
historically been a major source of functional AC and/or DC failures
and a significant reliability inhibiter.  This device demonstrates
the feasibility of electrical measurement of gate level line
foreshortening.

      The figure illustrates the new structure.  A rectangular thin
oxide region 1 is defined using standard recessed oxide isolation
processing.  After gate oxidation, the gate level 2 (typically poly)
is patterned into the horizontal 'bus' with a series of vertical
'tabs'.  This gate level figure is designed so that the vertical tabs
have varying amounts of overlap of the thin oxide rectangle.  The
tabs are positioned on both sides of the bus to discern overlap
differences due to misalignment between the gate and recessed oxide
levels.  A typical structure (value can vary) has polysilicon tabs
overlapping the thin oxide border by -0.5 um to +0.5 um in 0.1 um
increments (i.e., 11 tabs with -0.5 um, -.4 um, -.3 um, ...  0, ...
0.5 um).

      This foreshortening structure is physically positioned with the
polysilicon bus running horizontally at one test position and
vertically at another test site to accurately measure the extent of
foreshortening in both the vertical and horizontal direction...