Browse Prior Art Database

Low Power Partially Good Memory Chips by Fuse-Blowing Method

IP.com Disclosure Number: IPCOM000100417D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

By blowing fuses placed strategically in wordline interlock circuits of a partially good memory array, power is not sent to bad, unused circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 69% of the total text.

Low Power Partially Good Memory Chips by Fuse-Blowing Method

       By blowing fuses placed strategically in wordline
interlock circuits of a partially good memory array, power is not
sent to bad, unused circuits.

      Fig. 1 is a wordline interlock circuit diagram in a memory
architecture with each input/output (I/O) array having its own sense
timing circuit.  Fig. 2 shows a data select circuit input with fuse
F3 to be blown to reduce power used by a partially good memory chip.
Referring to Fig. 1, transistor T3 is a long, narrow depletion device
connected to supply voltage VDD and node N2.  Fuse F1 holds node N2
near ground potential.  Thus, transistors T1 and T2 are held off, and
the sources of transistors T10 and T11 are at ground potential.  A
signal from word line detect circuit WLD indicating array left active
is sent to the gate of transistor T10 and a signal indicating array
right active is sent to the gate of transistor T11.  Node NA is
driven by data select chip input pad IN shown in Fig. 2.  With fuses
F1 and F2 intact, the I/O array functions normally.

      If the chip is tested partially good, fuses F1, F2, and F3 are
blown to interupt power to bad quadrants.  When F1 is opened, node N2
is pulled to potential VDD through transistor T3.  Next, fuse F2 is
opened disconnecting precharge clock PC from node N3.  Precharge
connection PRE of amplifier 10 is then clamped to ground through
transistor T1.  Also, with node N2 at VDD, transistor...