Browse Prior Art Database

Modified Logic Test Hardware Enhancement

IP.com Disclosure Number: IPCOM000100424D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 96K

Publishing Venue

IBM

Related People

Koprowski, TJ: AUTHOR [+4]

Abstract

A Modified Logic Test (MLT) hardware enhancement is described in this article. It provides for the local generation of pseudo-random patterns for parallel or broadside application to VLSI LSSD devices using the Logic Test (LT) system, reducing overall test time and improving test quality. The disclosed LT hardware interfaces with the analog section of the existing LT system and does not require any additional LT logical functions.

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This is the abbreviated version, containing approximately 52% of the total text.

Modified Logic Test Hardware Enhancement

       A Modified Logic Test (MLT) hardware enhancement is
described in this article.  It provides for the local generation of
pseudo-random patterns for parallel or broadside application to VLSI
LSSD devices using the Logic Test (LT) system, reducing overall test
time and improving test quality.   The disclosed LT hardware
interfaces with the analog section of the existing LT system and does
not require any additional LT logical functions.

      It has been previously demonstrated that testing VLSI LSSD
devices with weighted pseudo-random patterns is beneficial in the
areas of test quality, test data generation and data management.
Throughput problems are noted in a manufacturing environment, due to
the lengthy test time required.  Deterministic test patterns, which
are usually fed to the LT are, in turn, applied to the device under
test only one pin at a time, a lengthy process.  The disclosed logic
tester hardware enhancements overcome this problem as described
below.

      New pseudo-random test patterns locally generated by the MLT
hardware as stimuli, are applied in parallel or broadside to the
device under test.  Product responses to these stimuli are then
loaded in parallel fashion and compressed in two signature analysis
stages, from which they are summarized.  A unique 32-bit signature is
generated for a particular part number after a given number (256) of
LSSD test pattern/response operations.  This unique signature is then
compared against a good machine simulation signature (good product).

      The MLT hardware enhancement consists of four sections: control
processor, broadside logic, modified driver card, and modified I/O
card.  Their functions are described in the following system
overview, with reference to the drawing.

      The MLT Control Processor 1 is a dedicated processor located in
the Drive Unit A gate 2.  It is loosely coupled to the UTS 3 and
is capable of executing 88 unique instructions at a clock rate of
12.8 MHz.  The data for the Control Processor is supplied by the UTS
from either EDMA 1 4 or EDMA 2 5.  The controls for the Control
Processor...