Browse Prior Art Database

Full LSSD Synchronizable Clock Divider

IP.com Disclosure Number: IPCOM000100428D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Desrosiers, B: AUTHOR [+2]

Abstract

The disclosed clock divider has the following features: 1. Divide by two the frequency of an input clock. 2. Provide a way to synchronize internal clocks on an external strobe referenced C_CLK that has to be active three periods after reset goes inactive. 3. Insure the non-overlap between the master and slave clocks respectively referenced as "B" and "C' in maximizing the usable time. 4. Be fully LSSD.

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Full LSSD Synchronizable Clock Divider

       The disclosed clock divider has the following features:
1.   Divide by two the frequency of an input clock.
2.   Provide a way to synchronize internal clocks on an external
strobe referenced C_CLK that has to be active three periods after
reset goes inactive.
3.   Insure the non-overlap between the master and slave clocks
respectively referenced as "B" and "C' in maximizing the usable time.
4.   Be fully LSSD.

      The proposed schematic and related timing in Figs. 1 and 2
address above points 1, 2 and 4.

      The non-overlap of C_CLK and B_CLK (internal clocks)
requirement is implemented according to the following.

      The circuit shown in Fig. 3 addresses point 3 above. It insures
the non-overlapping between C_CLK and B_CLK. In playing with the
delay differences between the delay blocks having different delays
referenced CQEL and CLMR we can maximize the usable time (Rising edge
of Bto falling edge of C).

      Moreover, the non-overlap is adjustable by adding more delay
blocks in the paths I or II.

      The timing figures and charts of circuit of Fig. 3 are given in
Fig. 4. As apparent from Fig. 4, we have a non-overlap between the
falling edge of C and the rising edge of the B of about .4 ns.

      Having the testability in mind at the very beginning of the
design, we built a "FULL LSSD" clock divider with a high test
coverage.

      Moreover, this design allow a G/C clock...