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Memory Error Correction/Detection Verification Scheme

IP.com Disclosure Number: IPCOM000100432D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Bond, AL: AUTHOR [+2]

Abstract

The error correction/detection (EC/D) circuitry guarantees 100% functional error correction and detection for single bit, double bit and specified multi-bit module failures. A verification scheme is implemented which creates all of these combinations of errors and confirms the detection, correction and proper error flag identification. Diagnostic verification for EC/D has always focused on modifying the data bits by some method of controlled read and write operations but has overlooked the check bits. In an EC/D hamming encoder/decoder scheme every bit is an integral part of the error bit detection and bit correction mechanism, whether data or check bits. By placing equal emphasis on the check bit error simulation the proper system data operation can be assured.

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Memory Error Correction/Detection Verification Scheme

       The error correction/detection (EC/D) circuitry
guarantees 100% functional error correction and detection for single
bit, double bit and specified multi-bit module failures.  A
verification scheme is implemented which creates all of these
combinations of errors and confirms the detection, correction and
proper error flag identification.  Diagnostic verification for EC/D
has always focused on modifying the data bits by some method of
controlled read and write operations but has overlooked the check
bits.  In an EC/D hamming encoder/decoder scheme every bit is an
integral part of the error bit detection and bit correction
mechanism, whether data or check bits.  By placing equal emphasis on
the check bit error simulation the proper system data operation can
be assured.

      The EC/D verification scheme utilizes all of the functional
blocks required for the normal error correction and detection
operations along with the unique functions for performing diagnostic.
 The components required for normal operation and system data
integrity verification are as follows:

      Standard EC/D Functional Blocks
1.  Hamming encoder to generate check bits for the system's write
data
2.  Hamming decoder to check and identify memory bit failures
3.  Exclusive OR gates to correct single bit errors identified by the
hamming decoder
4.  Error flags for notifying the system processor of a memory data
change, either correctable or non-correctable
5.  Syndrome data bits to uniquely identify a specific failure based
on an assigned error code

      EC/D Operational Enhancement Functional Blocks
1.  High and low data byte latches to retain data from byte write
operations where the system processor is allowed to continue after
the read portion is complete
2.  Inclusion of a syndrome register which can automatically capture
the bit failure pattern for system analysis
3.  Check bit latches for capturing check bits from read operations
for possible use in subsequent cycles

      Unique EC/D Control Blocks
1.  A system I/O mapped control register containing the following:
      a.   EC/D enable latch allows the system processor to control
when error correction and detection will function, but does not
inhibit/block the generation of check bits for any memory write
operation.  When enabled, the memory bus is checked for errors.
Single bit errors are corrected and all errors are flagged (interrupt
pulse) to the system processor. ...