Browse Prior Art Database

POS Register Extension With Multiple Chips, Each With Single Set of POS Registers

IP.com Disclosure Number: IPCOM000100442D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 154K

Publishing Venue

IBM

Related People

Sotolongo, H: AUTHOR

Abstract

This article describes a method for bringing extensions to the programmable option select (POS) registers of the MICRO CHANNEL* architecture of personal computer systems, when a group of chips is used in a card, and each chip can be operated singly with the conventional number of POS registers (8), and the conventional I/O addressing mechanism, or alternately can be operated as part of a group of chips and its POS registers can take on a different personality, capable of being addressed via the extension mechanism of the MICRO CHANNEL architecture. This affects the function using only two I/O pins per chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

POS Register Extension With Multiple Chips, Each With Single Set of POS Registers

       This article describes a method for bringing extensions
to the programmable option select (POS) registers of the MICRO
CHANNEL* architecture of personal computer systems, when a group of
chips is used in a card, and each chip can be operated singly with
the conventional number of POS registers (8), and the conventional
I/O addressing mechanism, or alternately can be operated as part of a
group of chips and its POS registers can take on a different
personality, capable of being addressed via the extension mechanism
of the MICRO CHANNEL architecture.  This affects the function using
only two I/O pins per chip.

      The MICRO CHANNEL architecture provides a mechanism for a bus
participant to extend its POS registers beyond the basic set of 8
bytes at addresses H'XXX0' through H'XXX7'. This is done by writing a
base address at H'XXX6' and writing a word of extension to H'XXX3'
and H'XXX4'.  This can be done as many times as required, up to the
limit specified by the MICRO CHANNEL architecture, each time with a
new base register, to load the required extension to H'XXX3' and
H'XXX4'.

      The mechanism provided in the MICRO CHANNEL works well when the
POS registers and the extensions reside in the same modules (same
card or same chip).  Extensions to this mechanism are required,
however, when multiple chips are placed on an adapter card, and each
chip is capable of working stand-alone or as part of a multiple set.
Speci fically, the POS register set should be capable of appearing as
either single chip POS registers, or as POS register extensions when
the chip is used in multiple chip applications.

      In the following description, references to writing I/O
addresses H'XXX0' through H'XXX7' assume that the MICRO CHANNEL has
been placed in set-up mode for that adapter, and therefore a set up
cycle is taking place in the MICRO CHANNEL.  Another assumption is
that MICRO CHANNEL signal CD SETUP has been logically provided to all
the chips, as described below, in the adapter card.

      Refer to the drawing for a block diagram of the card and chip
interconnection within the card.  As shown in the drawing, two
signals are used per chip to configure each chip to respond to
standard POS register access mechanism at addresses H'XXX0' through
H'XXX7' or to respond to the MICRO CHANNEL POS extension access
mechanism using I/O addresses H'XXX6', H'XXX3' and H'XXX4'.

      The signal POS_ENA_IN must be true to allow the setting of the
POS registers in that chip.  A chip with the signal false will not
recognize any MICRO CHANNEL set up cycles.

      In addition, two bits, one in the sub-address field of the POS
registers, the other in the device unique area of the POS registers,
are required.  In this description the first bit was defined in POS
register H'XXX6'.  This bit serves as a primary/extended (P/E) POS
designation.  T...