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Optimized Algorithm for Filtering T1 A/B Signalling Bits

IP.com Disclosure Number: IPCOM000100446D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 108K

Publishing Venue

IBM

Related People

Hsieh, DM: AUTHOR

Abstract

This article describes a technique for parallel processing any N channels firmware if the processor has data width (registers) of N bits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Optimized Algorithm for Filtering T1 A/B Signalling Bits

       This article describes a technique for parallel
processing any N channels firmware if the processor has data width
(registers) of N bits.

      The conventional method of filtering (qualifying) signalling
bits requires a significant amount processor bandwidth to qualify 48
individual T1 signalling bits. Therefore, there is not enough
processor bandwidth available to perform other tasks.  Consequently,
multiprocessor implementations have been required in the past.  The
method disclosed herein will group and qualify 16 signalling bits
simultane ously, thus reducing the processor bandwidth requirements
and increasing the overall performance.  The remaining processor
bandwidth allows additional tasks to be performed and can yield
simpler, less expensive designs.

      A T1 superframe consists of twelve frames of
information/signalling.  Each frame is comprised of 24 channels.  In
frames six and twelve each channel provides "robbed bit signalling",
denoted by "A" signalling bits and "B" signalling bits, respectively.
 Thus, there is a total of 48 signalling bits for the 24 channels for
each T1 superframe.  Before any action can be taken due to a
signalling bit value change (0 to 1, or 1 to 0), three consecutive
ones or zeros must be received.  This is a noise consideration.  This
algorithm filters multiple channels simultaneously, limited only by
the word length of the processor being utilized.  Prior
implementations utilized exhaustive test and branch algorithms on an
individual signalling bit basis.

      In the method of this disclosure, the T1 signalling bits for
multiple channels are filtered simultaneously utilizing common
logical operators (Exclusive-OR, AND, and NOT).  The logical flow
diagram for filtering signalling bits is shown in Fig. 1.  The
following facilities exist:
-    The network signalling bits facility is comprised of the
currently sampled network signalling bit values (0's or 1's) for each
of the 24 channels of a T1 superframe.
-    The Test Data #1, #2, and #3 facilities indicate (denoted by a 1
in the corresponding signalling bit locations) whether the filtered
signalling bits differ from the currently sampled...