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Shift Register Latch for Level-Sensitive Scan Designs Which Utilizes a Free-Running Clock to Minimize Clock Skew

IP.com Disclosure Number: IPCOM000100454D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Saxena, YB: AUTHOR [+2]

Abstract

A VLSI shift register latch (SRL) is disclosed for level-sensitive scan designs (LSSD) which does not require clock gating logic.

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Shift Register Latch for Level-Sensitive Scan Designs Which Utilizes a Free-Running Clock to Minimize Clock Skew

       A VLSI shift register latch (SRL) is disclosed for
level-sensitive scan designs (LSSD) which does not require clock
gating logic.

      In order to minimize skew in a clock distribution network for
level-sensitive scan logic designs, it is desirable to use
free-running clocks and eliminate the need for clock gating logic.
SRLs normally require two-phase, non-overlapping B and C clock pulses
in a LSSD. To prevent input data from being sampled by the input
latch, the C clock must remain low. This requires gating the C clock
and must be done before the clock becomes active. Utilization of
enable and feedback logic negates the need for SRL clock gating logic
required to choose between information on the data input line (new
data) and feedback information from the output latch (old data). The
new approach allows the decision between old and new data a set-up
time before the C clock goes inactive. This allows more logic time
for the decision. Furthermore, the new system can be implemented
without affecting the clock distribution network.

      Solid lines in the figure show the present SRL design. The
dotted lines show the newly integrated enable and feedback logic
utilized to eliminate the need for gated clock pulses. The enable
line is used to select either old data or new data when the C clock
is high. If the enable line is low, p channel trans...