Browse Prior Art Database

Model Ordering for Compiled Enhanced Functional Simulator

IP.com Disclosure Number: IPCOM000100468D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 8 page(s) / 336K

Publishing Venue

IBM

Related People

Bargh, JF: AUTHOR

Abstract

This process efficiently converts a parallel hardware description to a serial description for logic simulation. The problem solved is to quickly produce an efficient simulation model.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 18% of the total text.

Model Ordering for Compiled Enhanced Functional Simulator

       This process efficiently converts a parallel hardware
description to a serial description for logic simulation. The problem
solved is to quickly produce an efficient simulation model.

      A hardware description at the Register Transfer Language (RTL)
level has massive amounts of parallelism in the model.  The goal of a
logic simulator is to accurately simulate this model as quickly as
possible.  The fastest technique available on a general-purpose
machine is zero-delay cycle simulation.  The model-ordering
processing converts an RTL description for such a compiled enhanced
functional simulator (CEFS) with the following constraints:
1.   The output is a serial model with the structure of the model
still correct.  That is, the relationship between conditional
statements (IFs and CGOTOs) and their target statements must be
maintained.
2.   The model must be correctly signal ordered.  All of the
assignments to a signal bit must occur before any reference to that
bit.
3.   The model must be segmented into clock sections.  Each clock
section is further broken into a signal block section and latch block
section.  At the beginning of each major clock cycle, the signal
block will be run by CEFS to generate the signals.  The latch block
will be run on the last minor cycle of each clock to generate the
next value for that clock's latches.
4.   The generated model must simulate as quickly as possible.  RTL
statements are assigned to the slowest clock section possible that
will still give correct behavior.  The number of serialization flags
generated by model ordering must be kept to a minimum.  These flags,
called guard bits, are used when related pieces of the parallel model
must be separated in the output serial model.  For example, a
decision statement may be placed in a signal block and some of its
targets may be placed in a latch block.
5.   Model ordering must run reasonably quickly.  In particular, the
CPU time spent in this process must not grow polynomially as the
models get larger.  It will be shown that the time grows nearly
linearly with model size.

      The only comparable design for model ordering is the signal
ordering algorithm.  Model ordering has the following advantages over
signal ordering:
1.   The model is segmented into signal blocks and latch blocks to
allow faster simulation.
2.   The use of guard bits to control serialization is greatly
reduced.  There is only 1 type of guard bit in model ordering
compared to 3 different types in signal ordering.
3.   The CPU time spent in signal ordering is proportional to n*ln(n)
where n is the number of statements in the model.  Model ordering
takes n*ln(ln(n)) which is significantly less for large models.

      The old signal ordering design basically makes repetitive
passes over the RTL model to build the serial model.  This has the
disadvantage that information is hidd...