Browse Prior Art Database

High-Performance Register-to-Register Transfer Instructions

IP.com Disclosure Number: IPCOM000100472D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Nadas, SJ: AUTHOR [+2]

Abstract

Disclosed is a hardware mechanism that permits register-to-register transfer instructions to be executed in the decode cycle; this is a cycle earlier than in previous machines. The mechanism permits faster execution by allowing the same physical register to be referenced by multiple instructions if (and only if) the second and subsequent references are from register-to-register transfer instructions. The mechanism also conserves physical registers from the register pool by allowing them to be shared.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-Performance Register-to-Register Transfer Instructions

       Disclosed is a hardware mechanism that permits
register-to-register transfer instructions to be executed in the
decode cycle; this is a cycle earlier than in previous machines.  The
mechanism permits faster execution by allowing the same physical
register to be referenced by multiple instructions if (and only if)
the second and subsequent references are from register-to-register
transfer instructions.  The mechanism also conserves physical
registers from the register pool by allowing them to be shared.

      Presupposed is a highly parallel, pipelined processor with
out-of- sequence execution of instructions via multiple execution
units of different types.  Assumed is a set of N physical registers
which are used to implement various architected registers.  Also
assumed is a branching mechanism that allows parallel execution of
multiple conditional instruction streams.

      Previous designs have used control structures including an
array to hold the status of the physical registers pool, an array to
contain the logical to physical register mapping at decode time, and
an array to hold a copy of the mapping array for handling
conditionally issued instructions. Previous designs have always
allocated a new physical register to every instruction that writes a
register; as a result, all mapping array entries were unique.

      In this invention, the load register instruction can be
executed in the decode cycle by copying the correct mapping array
entry rather than taking a cycle in an execution unit to move data
from one physical register to another.  This approach implies that
multiple mapping array entries may contain the same physical register
identification.

      The mechanism consists of a structure called the Shared
Physical Register Table (SRT) shown in the figure.  When physical
registers are shared, this SRT records information about the status
of the shared physical registers.  T...