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Improved Time Interval Digitizer

IP.com Disclosure Number: IPCOM000100487D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Hrinya, SJ: AUTHOR [+3]

Abstract

The improved time interval digitizer uses a stable reference oscillator, a counter, and two interpolators (Fig. 1) to perform a highly accurate time interval-to-digital conversion. The input logic converts the start and stop signals into complementary pulses of fixed width W. This logic is designed to minimize the delay in the signal path, so that the leading edge of the pulses has minimum jitter with respect to the input pulses. The positive pulses control a coarse counter, and the negative pulses enable the gated oscillators within the interpolator. The interpolator (Fig. 2) consists of a gated oscillator, RF amplifier, power splitters, phase detectors, filters, flash A/D converters and additional circuitry for a gated frequency locked loop.

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Improved Time Interval Digitizer

       The improved time interval digitizer uses a stable
reference oscillator, a counter, and two interpolators (Fig. 1) to
perform a highly accurate time interval-to-digital conversion.  The
input logic converts the start and stop signals into complementary
pulses of fixed width W.  This logic is designed to minimize the
delay in the signal path, so that the leading edge of the pulses has
minimum jitter with respect to the input pulses.  The positive pulses
control a coarse counter, and the negative pulses enable the gated
oscillators within the interpolator.  The interpolator (Fig. 2)
consists of a gated oscillator, RF amplifier, power splitters, phase
detectors, filters, flash A/D converters and additional circuitry for
a gated frequency locked loop.

      The coarse counter is enabled and disabled by the start and
stop pulses and counts one phase of the reference oscillator.  Since
the start/stop pulses are asynchronous with the oscillator, a race
condition could arise whenever the setup/hold times of the input
latches are not met.  This plus or minus one uncertainty in the
coarse count is detected by the race detection logic which sets two
race bits.  The output logic combines the coarse counter output, the
race bits, and the difference between the start and stop interpolator
outputs to produce the digitized value of the time interval.

      The interpolator (Fig. 2) measures the relative phase between
the gated a...