Browse Prior Art Database

Squarer - Multiplier

IP.com Disclosure Number: IPCOM000100491D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Wallin, GW: AUTHOR

Abstract

A Squarer-Multiplier reduces the hardware required to perform a multiplication by replacing the multiplier by an adder and logic to do a squaring function. The idea behind the design emanates from noticing that: A*B = ((A+B) /2)**2 - ((A-B) /2)**2

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Squarer - Multiplier

       A Squarer-Multiplier reduces the hardware required to
perform a multiplication by replacing the multiplier by an adder and
logic to do a squaring function.
      The idea behind the design emanates from noticing that:
           A*B = ((A+B) /2)**2 - ((A-B) /2)**2

      The A and B operands to be multiplied are first added together,
then subtracted (either A-B or B-A).  Those results are shifted one
bit, and run through a "Squarer" circuitry.  These squared results
are then subtracted (the second from the first).  Fig. 1 shows a data
flow for this process.

      An implementation of a "Squarer" to square a binary number is
provided in Fig. 2.

      From the above equation, the table provided in Fig. 3 is
generated.  It shows the logical "ANDing" term sums which need to be
generated to implement each bit of the squarer output.