Browse Prior Art Database

Integrated Pseudo SCR Circuit

IP.com Disclosure Number: IPCOM000100512D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

DeMoor, MK: AUTHOR [+3]

Abstract

Disclosed is a pseudo SCR which is used in an integrated circuit. It uses low current PNP and NPN devices in conjunction with a high current DMOS device to achieve the SCR latching effect along with high current capability.

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Integrated Pseudo SCR Circuit

       Disclosed is a pseudo SCR which is used in an integrated
circuit.  It uses low current PNP and NPN devices in conjunction with
a high current DMOS device to achieve the SCR latching effect along
with high current capability.

      Commonly used in discrete SCR circuits is the combination PNP
and NPN circuit shown in the figure as "SCR ELEMENT".  In an
integrated power chip, low current lateral PNP and NPN devices are
available along with high current DMOS devices.  The circuit
presented here uses these devices in a unique way to form an
integrated high current pseudo SCR.  Also included is a logic level
output which indicates the state of the pseudo SCR.

      In the figure, Q2 and Q3 form the SCR element.  The current is
limited by R2 to levels compatible with integrated NPN and lateral
PNP devices.  The SCR element controls a driver formed by Q4, R5 and
Q5.  Q5 is a power DMOS and carries the bulk of the pseudo SCR
current.

      When the SCR is triggered, Q2 and Q3 latch on.  This turns off
Q4 and turns on Q5.  Q5 then pulls down VIN and carries the full IIN
current.  If the input VIN is removed and then reapplied, the pseudo
SCR is reset and Q5 is turned off.  Zener diodes Z1 and Z2 prevent
the gate of the DMOS devices from exceeding the gate to source
breakdown voltage.