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Browse Prior Art Database

Bus Controller for Color Monitor

IP.com Disclosure Number: IPCOM000100540D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Santitoro, RT: AUTHOR

Abstract

Disclosed is an architecture in which the IIC protocol has been implemented in microcode on a digitally controlled color monitor. The protocol uses only 2 input ports and 2 output ports on a microcontroller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bus Controller for Color Monitor

       Disclosed is an architecture in which the IIC protocol
has been implemented in microcode  on a digitally controlled color
monitor.  The protocol uses only 2 input ports and 2 output ports on
a microcontroller.

      The system consists of 2 octuple 6-bit D/A converters, a
deflection processor, and a 2kbit NVRAM all of which are IIC
compatible.  The system also has a microcontroller which is not IIC
compatible.

      The deflection processor has internal D/A converters which are
used to control: G2 Fine, Horizontal Centering, Height, Vertical
Linearity, Vertical S-Correction, Vertical Centering, Vertical EHT
Compensation (5-bit resolution), Width, East/West Pincushion
Correction, East/West Cornering, Trapezium, Horizontal EHT
Compensation (5-bit resolution).

      Six of the eight D/A converters are used to control the
following adjustments: Green Gain 1, Red Gain 1, Blue Gain 1, Blue
Gain 2, Red Gain 2, Green Gain 2.  By using 2 Gain D/A converters per
color, 7 bits (128 steps) of resolution is achieved.

      Each D/A converter in the second octuple D/A is used for the
following adjustments: Green Cutoff Fine, Red Cutoff Fine, Blue
Cutoff Fine, Green Cutoff Coarse, Red Cutoff Coarse, Blue Cutoff
Course, G2 Coarse, Brightness Override.

      Upon power up, the microcontroller does not know whether the
NVRAM contains valid set-up information.  Prior to testing the
monitor, the NVRAM will contain invalid data. It was therefore
necessary to create a mechanism which would allow the microcontroller
to determine this.  A 1-byte code is used.  Data is valid whenever
this byte has a fixed value; otherwise, the NVRAM data will not be
used.

      Since it is possible that other parameters may be added which
are not required for monitor operation, a data pointer byte is used
to point to the address where the Front of Screen (FOS) data begins.

      A refresh delay byte determines the amount of time that the
microcontroller will delay before updating (refreshing) the D/A
converters.

      FRONT OF SCREEN DATA: Front-of-screen data bytes consist of 3
sets of chip addresses, subaddresses, and data values corresponding
to the 3 ICs in the system.  The chip addresses and subaddresses are
fixed values but the DAC data bytes may be programmed.

      MICROCODE FUNCTIONAL DESCRIPTION: Upon a Power On Reset (POR),
the following steps are executed:
1. Read known NVRAM location to determine whether stored data is
valid.  Two possible conditions may occur depending on the value of
the byte.
a. Byte 0 fixed value -- data is valid; continue using NVRAM as data
source.
           b. Byte 0 not equal to fixed value -- data is invalid; use
data stored in data space ROM of the microcontroller and disregard
all data in NVRAM.  The data sto...