Browse Prior Art Database

Dual Mode of Operation for Status Register

IP.com Disclosure Number: IPCOM000100546D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Somyak, TJ: AUTHOR

Abstract

Disclosed is an implementation of a status register that can be cleared on a bit-by-bit basis or written to on a word basis.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dual Mode of Operation for Status Register

       Disclosed is an implementation of a status register that
can be cleared on a bit-by-bit basis or written to on a word basis.

      In many applications it is desirable to have a register that
has the capability to be modified on a bit by bit basis.  Examples of
this are an exception status register or an interrupt status register
where the system processor is required to service or otherwise
acknowledge DUAL MODE OF the occurrence of an event and then clear
only the corresponding bit in the register.  The problem with these
registers is that the processor has difficulty testing them.
Programmers writing diagnostics for these registers are faced with
the task of finding ways to set the individual bits, verifying that
they are set, clearing them, and verifying that they have been
cleared.  The code required for this testing is often inefficient.
It would be a great advantage to be able to simply write a data
pattern to the register and read it back for verification.  This
article describes a register implementation that can be cleared on a
bit-by-bit basis and can be efficiently tested.

      In order to facilitate efficient testing, a scheme was invented
where the register would have two modes of operation.  In normal
operation, the register latches a single bit of system status and
holds it until that bit is specifically cleared by the system
processor.  For ease of programming, the programmer merely needs to
write a logical 1 to a bit location in order to clear that particular
bit.  In this way, if it is desirable to clear the entire register,
the value read from the register is simply written back. When testing...