Browse Prior Art Database

Bipolar ECC for a Personal Computer

IP.com Disclosure Number: IPCOM000100551D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR [+4]

Abstract

This article describes a bipolar chip designed for an error correction code (ECC) function for a 32-bit microprocessor such as an Intel 80386.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Bipolar ECC for a Personal Computer

       This article describes a bipolar chip designed for an
error correction code (ECC) function for a 32-bit microprocessor such
as an Intel 80386.

      Several "high end" personal computers require ECC.  A solution
is to employ two integrated device technology (IDT) ECC modules and
ten "245" bipolar buffer modules.  The bipolar design as implemented
herein contains a two-port or a flow-through design.  The key is that
the data flows through the ECC function with minimal interruption and
with bipolar drive.  The control of the data bus is much simpler and
less prone to bus contention problems.

      The fact that this is a bipolar design implies the integration
of the drivers.  The insertion delay of the buffers is eliminated
because they are integrated with the ECC functional island.

      The drawing shows the chip of this disclosure in block diagram.
 It is implemented in bipolar technology.  It will operate at about
20 ns for data to correct.  Further, the controls are designed to be
compatible with the memory controller.