Browse Prior Art Database

Power-On Self Testing for Multi-Tasking Personal Computers

IP.com Disclosure Number: IPCOM000100559D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 168K

Publishing Venue

IBM

Related People

Randall, DL: AUTHOR

Abstract

A technique is described whereby power-on self testing (POST) of multi- tasking personal computers enable adapters and devices to be optimally tested. The design is such that a single call to a subsystem POST test code will test and initialize the entire subsystem. The concept describes the use of POST in small computer subsystem interface (SCSI) applications consisting of up to four adapters and up to sixty devices. However, the concept is not confined to SCSI subsystem implementation.

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This is the abbreviated version, containing approximately 37% of the total text.

Power-On Self Testing for Multi-Tasking Personal Computers

       A technique is described whereby power-on self testing
(POST) of multi- tasking personal computers enable adapters and
devices to be optimally tested.  The design is such that a single
call to a subsystem POST test code will test and initialize the
entire subsystem.  The concept describes the use of POST in small
computer subsystem interface (SCSI) applications consisting of up to
four adapters and up to sixty devices.  However, the concept is not
confined to SCSI subsystem implementation.

      Typically, POST code has relied on procedures supplied by the
compatibility mode BIOS (CBIOS) to handle portions of I/O
interfacing.  However, using CBIOS in a POST environment provides
only a single thread design and only one command is processed at a
time. Therefore, the time involved in testing up to sixty devices
distributed among four adapters is considered excessive.  The concept
described herein utilizes multiple thread techniques, similar to
those employed in large systems. A thread in this context is defined
as the steps involved in issuing a command to a device, handling the
response to the command by the device and ensuring that command
completion is timely. The approach relies on the hardware capability
of carrying on concurrent conversations with devices attached to the
adapter.  The POST testing consists of four major operations:
       1. Supervisor or Test Dispatcher
       2. Test Subroutine
       3. Device Interrupt Handling
       4. Event Timing

      Supervisor: The supervisor is given the responsibility to
continuously scan the device blocks (described later) searching for
idle devices.  Once a device is determined to be idle, the State
information is used to direct the program flow to the appropriate
test subroutine.  The supervisor continues looping through the device
blocks until it has been determined that all devices have completed
their prescribed test phases.  Control is then passed to subroutines
that display errors that occurred during testing.  A data table is
then formulated to be used by the systems CBIOS and advance BIOS
(ABIOS) interfaces.  Upon completion of the data table, control is
returned to the mainline system POST code to complete the remainder
of the system's initialization.

      Test Subroutines: It has been determined that regardless of the
device type, operations required to test the device and to leave it
in an initialized state involved similar command sequences. The
operations can be split into logical test states resulting in a State
Machine strategy.  Each test subroutine interrogates information in
the device block to determine whether a command has been issued and
has been completed or if a command needs to be issued.  If required,
a command is issued to the device currently addressed, a timer is
initialized for the expected command duration, the device block is
marked to i...