Browse Prior Art Database

Using Partially Good Data Cache Vlsi Chips in an Environment Of Flexible System Configuration

IP.com Disclosure Number: IPCOM000100575D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 123K

Publishing Venue

IBM

Related People

Jaber, T: AUTHOR [+4]

Abstract

This invention solves the problem of increased system cost due to the low yield of VLSI data cache chips by suggesting a technique of using partially good data cache chips instead of discarding them. The technique also boosts the system reliability and its uptime by allowing a hardware-adaptable, software-controlled, limited data cache access configuration of the processor. A total field failure can always be avoided by programming the processor hardware to patch around the failing data cache hardware. The concept can be virtually extended to any partially functional VLSI chip and is not restricted to data cache chips only.

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Using Partially Good Data Cache Vlsi Chips in an Environment Of Flexible System Configuration

       This invention solves the problem of increased system
cost due to the low yield of VLSI data cache chips by suggesting a
technique of using partially good data cache chips instead of
discarding them.  The technique also boosts the system reliability
and its uptime by allowing a hardware-adaptable, software-controlled,
limited data cache access configuration of the processor.  A total
field failure can always be avoided by programming the processor
hardware to patch around the failing data cache hardware.  The
concept can be virtually extended to any partially functional VLSI
chip and is not restricted to data cache chips only.

      One of the most severe problems in the manufacturing of VLSI
chips is the low yield of defect-free chips.  In many cases, it is
not uncommon to have yields as low as 2% to 5% and, in worse cases,
the yield is simply 0%.  The low yield problem is very costly because
it ultimately leads to the discarding of large volumes of partially
good VLSI chips. This article describes a technique of how to salvage
partially good chips and how to use them in systems configured to
account for defects present on these chips and still deliver a
cost-effective, acceptable performance, although slightly downgraded
from a fully functional system.

      In our particular case, the system is a processor built with up
to ten VLSI chips, four of which can be data cache VLSI chips.

      The 64K byte data cache design, incorporating 4-way set
associativity, is contained on 4 identical VLSI chips, each chip
having 1/4 of the total cache size.

      These data cache chips might have a very poor yield when all
four sets on each chip have to be defect-free.  The yield is markedly
higher if only three, two or one set is defect-free.

      A processor card is built by mixing and matching the good array
sets (see Fig. 1).  Thus, a perfect system has all data cache chips
defect-free and is configured for maximum data cache use, whereas
partially good data cache chips offer a system with only one, two or
three (out of four) good sets.

      Each VLSI chip has a COP (Common On-chip Processor) controller
which is in charge of running and controlling self-test functions on
each of the VLSI chips upon receiving a sequence of commands from the
OCS (On Card Sequencer, 8051 INTEL controller) over the serially
controlled COP bus.

      In the pro...