Browse Prior Art Database

Pulse Combining Network

IP.com Disclosure Number: IPCOM000100581D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Marshall, MG: AUTHOR [+3]

Abstract

A circuit is shown for generating true and complement phase of a signal with negligible skew using edge-triggered latches.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Pulse Combining Network

       A circuit is shown for generating true and complement
phase of a signal with negligible skew using edge-triggered latches.

      Prior art true and complement circuit outputs have appreciable
skew. By utilizing the circuit shown in block diagram form in Fig. 1,
with a multiplicity of input signals shown in Fig. 2, true and
complement output waveforms are provided with no appreciable skew
between the two outputs. The circuit has a number of different
possible applications, i.e., frequency divider, frequency multiplier,
and waveform shaping.

      The signal PRESET resets one edge-trigger latch to zero and
sets the other latch to one. Each clock chopper circuit outputs a
pulse on the rising (or falling) edge of its input signal. Pulses
from any number of clock choppers are ORed together, such that each
pulse clocks the edge-triggered latches, causing them to toggle. The
latches are identical in every way except that they are initialized
to complementary states. They are designed such that the delay in
clocking a data value of one is the same as the delay for clocking a
zero. Thus, the problem of skew is avoided.

      The PRESET pulse shown in the timing diagram (Fig. 2) sets the
TRUE output to one and the COMPLEMENT output to a zero. An INPUT
change from 0 to 1 generates a pulse which causes the output to
change. One advantage of the circuit is its ability to provide a
waveform "shaping" function. When INPUT 2 is just the co...